mirror of
https://github.com/sle118/squeezelite-esp32.git
synced 2025-12-08 12:37:01 +03:00
851 lines
32 KiB
C
851 lines
32 KiB
C
/* GDS Example
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This example code is in the Public Domain (or CC0 licensed, at your option.)
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Unless required by applicable law or agreed to in writing, this
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software is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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CONDITIONS OF ANY KIND, either express or implied.
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*/
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#include <string.h>
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#include <stdlib.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/timers.h"
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#include "freertos/queue.h"
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#include "esp_task.h"
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#include "esp_log.h"
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#include "driver/gpio.h"
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#include "driver/i2c.h"
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#include "driver/spi_master.h"
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#include "gpio_exp.h"
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#define GPIO_EXP_INTR 0x100
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#define GPIO_EXP_WRITE 0x200
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/*
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shadow register is both output and input, so we assume that reading to the
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ports also reads the value set on output
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*/
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typedef struct gpio_exp_s {
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uint32_t first, last;
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int intr;
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bool intr_pending;
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struct {
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struct gpio_exp_phy_s phy;
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spi_device_handle_t spi_handle;
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};
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uint32_t shadow, pending;
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TickType_t age;
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SemaphoreHandle_t mutex;
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uint32_t r_mask, w_mask;
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uint32_t pullup, pulldown;
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struct gpio_exp_isr_s {
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gpio_isr_t handler;
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void *arg;
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TimerHandle_t timer;
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} isr[32];
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struct gpio_exp_model_s const *model;
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} gpio_exp_t;
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typedef struct {
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enum { ASYNC_WRITE } type;
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int gpio;
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int level;
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gpio_exp_t *expander;
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} queue_request_t;
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static const char TAG[] = "gpio expander";
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static void IRAM_ATTR intr_isr_handler(void* arg);
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static gpio_exp_t* find_expander(gpio_exp_t *expander, int *gpio);
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static esp_err_t mpr121_init(gpio_exp_t* self);
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static uint32_t mpr121_read(gpio_exp_t* self);
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static void mpr121_write(gpio_exp_t* self);
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static void pca9535_set_direction(gpio_exp_t* self);
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static uint32_t pca9535_read(gpio_exp_t* self);
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static void pca9535_write(gpio_exp_t* self);
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static uint32_t pca85xx_read(gpio_exp_t* self);
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static void pca85xx_write(gpio_exp_t* self);
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static esp_err_t mcp23017_init(gpio_exp_t* self);
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static void mcp23017_set_pull_mode(gpio_exp_t* self);
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static void mcp23017_set_direction(gpio_exp_t* self);
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static uint32_t mcp23017_read(gpio_exp_t* self);
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static void mcp23017_write(gpio_exp_t* self);
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static esp_err_t mcp23s17_init(gpio_exp_t* self);
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static void mcp23s17_set_pull_mode(gpio_exp_t* self);
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static void mcp23s17_set_direction(gpio_exp_t* self);
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static uint32_t mcp23s17_read(gpio_exp_t* self);
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static void mcp23s17_write(gpio_exp_t* self);
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static void service_handler(void *arg);
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static void debounce_handler( TimerHandle_t xTimer );
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static esp_err_t i2c_write(uint8_t port, uint8_t addr, uint8_t reg, uint32_t data, int len);
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static uint32_t i2c_read(uint8_t port, uint8_t addr, uint8_t reg, int len);
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static spi_device_handle_t spi_config(struct gpio_exp_phy_s *phy);
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static esp_err_t spi_write(spi_device_handle_t handle, uint8_t addr, uint8_t reg, uint32_t data, int len);
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static uint32_t spi_read(spi_device_handle_t handle, uint8_t addr, uint8_t reg, int len);
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static const struct gpio_exp_model_s {
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char *model;
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gpio_int_type_t trigger;
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esp_err_t (*init)(gpio_exp_t* self);
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uint32_t (*read)(gpio_exp_t* self);
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void (*write)(gpio_exp_t* self);
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void (*set_direction)(gpio_exp_t* self);
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void (*set_pull_mode)(gpio_exp_t* self);
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} registered[] = {
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{ .model = "mpr121",
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.trigger = GPIO_INTR_LOW_LEVEL,
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.init = mpr121_init,
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.read = mpr121_read,
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.write = mpr121_write, },
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{ .model = "pca9535",
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.trigger = GPIO_INTR_LOW_LEVEL,
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.set_direction = pca9535_set_direction,
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.read = pca9535_read,
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.write = pca9535_write, },
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{ .model = "pca85xx",
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.trigger = GPIO_INTR_LOW_LEVEL,
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.read = pca85xx_read,
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.write = pca85xx_write, },
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{ .model = "mcp23017",
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.trigger = GPIO_INTR_LOW_LEVEL,
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.init = mcp23017_init,
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.set_direction = mcp23017_set_direction,
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.set_pull_mode = mcp23017_set_pull_mode,
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.read = mcp23017_read,
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.write = mcp23017_write, },
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{ .model = "mcp23s17",
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.trigger = GPIO_INTR_LOW_LEVEL,
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.init = mcp23s17_init,
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.set_direction = mcp23s17_set_direction,
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.set_pull_mode = mcp23s17_set_pull_mode,
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.read = mcp23s17_read,
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.write = mcp23s17_write, },
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};
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static EXT_RAM_ATTR uint8_t n_expanders;
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static EXT_RAM_ATTR QueueHandle_t message_queue;
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static EXT_RAM_ATTR gpio_exp_t expanders[4];
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static EXT_RAM_ATTR TaskHandle_t service_task;
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/******************************************************************************
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* Retrieve base from an expander reference
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*/
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uint32_t gpio_exp_get_base(gpio_exp_t *expander) {
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return expander->first;
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}
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/******************************************************************************
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* Retrieve reference from a GPIO
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*/
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gpio_exp_t *gpio_exp_get_expander(int gpio) {
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int _gpio = gpio;
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return find_expander(NULL, &_gpio);
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}
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/******************************************************************************
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* Create an I2C expander
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*/
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gpio_exp_t* gpio_exp_create(const gpio_exp_config_t *config) {
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gpio_exp_t *expander = expanders + n_expanders;
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if (config->base < GPIO_NUM_MAX || n_expanders == sizeof(expanders)/sizeof(gpio_exp_t)) {
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ESP_LOGE(TAG, "Base %d GPIO must be at least %d for %s or too many expanders %d", config->base, GPIO_NUM_MAX, config->model, n_expanders);
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return NULL;
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}
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// See if we know that model (expanders is zero-initialized)
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for (int i = 0; !expander->model && i < sizeof(registered)/sizeof(struct gpio_exp_model_s); i++) {
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if (strcasestr(config->model, registered[i].model)) expander->model = registered + i;
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}
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// well... try again
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if (!expander->model) {
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ESP_LOGE(TAG, "Unknown GPIO expansion chip %s", config->model);
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return NULL;
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}
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memcpy(&expander->phy, &config->phy, sizeof(struct gpio_exp_phy_s));
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// try to initialize the expander if required
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if (expander->model->init && expander->model->init(expander) != ESP_OK) {
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ESP_LOGE(TAG, "Cannot create GPIO expander %s, check i2c/spi configuration", config->model);
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return NULL;
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}
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n_expanders++;
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expander->first = config->base;
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expander->last = config->base + config->count - 1;
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expander->intr = config->intr;
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expander->mutex = xSemaphoreCreateMutex();
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// create a task to handle asynchronous requests (only write at this time)
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if (!message_queue) {
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// we allocate TCB but stack is static to avoid SPIRAM fragmentation
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StaticTask_t* xTaskBuffer = (StaticTask_t*) heap_caps_malloc(sizeof(StaticTask_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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static EXT_RAM_ATTR StackType_t xStack[4*1024] __attribute__ ((aligned (4)));
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message_queue = xQueueCreate(4, sizeof(queue_request_t));
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service_task = xTaskCreateStatic(service_handler, "gpio_expander", sizeof(xStack), NULL, ESP_TASK_PRIO_MIN + 1, xStack, xTaskBuffer);
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}
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// set interrupt if possible
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if (config->intr >= 0) {
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gpio_pad_select_gpio(config->intr);
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gpio_set_direction(config->intr, GPIO_MODE_INPUT);
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switch (expander->model->trigger) {
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case GPIO_INTR_NEGEDGE:
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case GPIO_INTR_LOW_LEVEL:
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gpio_set_pull_mode(config->intr, GPIO_PULLUP_ONLY);
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break;
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case GPIO_INTR_POSEDGE:
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case GPIO_INTR_HIGH_LEVEL:
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gpio_set_pull_mode(config->intr, GPIO_PULLDOWN_ONLY);
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break;
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default:
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gpio_set_pull_mode(config->intr, GPIO_PULLUP_PULLDOWN);
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break;
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}
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gpio_set_intr_type(config->intr, expander->model->trigger);
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gpio_isr_handler_add(config->intr, intr_isr_handler, expander);
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gpio_intr_enable(config->intr);
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}
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ESP_LOGI(TAG, "Create GPIO expander %s at base %u with intr %d at @%x on port/host %d/%d", config->model, config->base, config->intr, config->phy.addr, config->phy.port, config->phy.host);
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return expander;
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}
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/******************************************************************************
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* Add ISR handler for a GPIO
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*/
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esp_err_t gpio_exp_isr_handler_add(int gpio, gpio_isr_t isr_handler, uint32_t debounce, void *arg, struct gpio_exp_s *expander) {
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if (gpio < GPIO_NUM_MAX && !expander) return gpio_isr_handler_add(gpio, isr_handler, arg);
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if ((expander = find_expander(expander, &gpio)) == NULL) return ESP_ERR_INVALID_ARG;
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expander->isr[gpio].handler = isr_handler;
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expander->isr[gpio].arg = arg;
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if (debounce) expander->isr[gpio].timer = xTimerCreate("gpioExpDebounce", pdMS_TO_TICKS(debounce),
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pdFALSE, expander->isr + gpio, debounce_handler );
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return ESP_OK;
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}
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/******************************************************************************
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* Remove ISR handler for a GPIO
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*/
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esp_err_t gpio_exp_isr_handler_remove(int gpio, struct gpio_exp_s *expander) {
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if (gpio < GPIO_NUM_MAX && !expander) return gpio_isr_handler_remove(gpio);
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if ((expander = find_expander(expander, &gpio)) == NULL) return ESP_ERR_INVALID_ARG;
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if (expander->isr[gpio].timer) xTimerDelete(expander->isr[gpio].timer, portMAX_DELAY);
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memset(expander->isr + gpio, 0, sizeof(struct gpio_exp_isr_s));
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return ESP_OK;
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}
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/******************************************************************************
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* Set GPIO direction
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*/
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esp_err_t gpio_exp_set_direction(int gpio, gpio_mode_t mode, gpio_exp_t *expander) {
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if (gpio < GPIO_NUM_MAX && !expander) return gpio_set_direction(gpio, mode);
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if ((expander = find_expander(expander, &gpio)) == NULL) return ESP_ERR_INVALID_ARG;
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xSemaphoreTake(expander->mutex, pdMS_TO_TICKS(portMAX_DELAY));
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if (mode == GPIO_MODE_INPUT) {
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expander->r_mask |= 1 << gpio;
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expander->shadow = expander->model->read(expander);
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expander->age = ~xTaskGetTickCount();
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} else {
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expander->w_mask |= 1 << gpio;
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}
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if (expander->r_mask & expander->w_mask) {
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xSemaphoreGive(expander->mutex);
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ESP_LOGE(TAG, "GPIO %d on expander base %u can't be r/w", gpio, expander->first);
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return ESP_ERR_INVALID_ARG;
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}
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// most expanders want unconfigured GPIO to be set to output
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if (expander->model->set_direction) expander->model->set_direction(expander);
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xSemaphoreGive(expander->mutex);
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return ESP_OK;
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}
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/******************************************************************************
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* Get GPIO level with cache
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*/
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int gpio_exp_get_level(int gpio, int age, gpio_exp_t *expander) {
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if (gpio < GPIO_NUM_MAX && !expander) return gpio_get_level(gpio);
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if ((expander = find_expander(expander, &gpio)) == NULL) return -1;
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uint32_t now = xTaskGetTickCount();
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// return last thing we had if we can't get the mutex
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if (xSemaphoreTake(expander->mutex, pdMS_TO_TICKS(50)) == pdFALSE) {
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ESP_LOGW(TAG, "Can't get mutex for GPIO %d", expander->first + gpio);
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return (expander->shadow >> gpio) & 0x01;
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}
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// re-read the expander if data is too old
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if (age >= 0 && now - expander->age >= pdMS_TO_TICKS(age)) {
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uint32_t value = expander->model->read(expander);
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expander->pending |= (expander->shadow ^ value) & expander->r_mask;
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expander->shadow = value;
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expander->age = now;
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}
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// clear pending bit
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expander->pending &= ~(1 << gpio);
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xSemaphoreGive(expander->mutex);
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ESP_LOGD(TAG, "Get level for GPIO %u => read %x", expander->first + gpio, expander->shadow);
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return (expander->shadow >> gpio) & 0x01;
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}
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/******************************************************************************
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* Set GPIO level with cache
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*/
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esp_err_t gpio_exp_set_level(int gpio, int level, bool direct, gpio_exp_t *expander) {
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if (gpio < GPIO_NUM_MAX && !expander) return gpio_set_level(gpio, level);
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if ((expander = find_expander(expander, &gpio)) == NULL) return ESP_ERR_INVALID_ARG;
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uint32_t mask = 1 << gpio;
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// very limited risk with lack of semaphore here
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if ((expander->w_mask & mask) == 0) {
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ESP_LOGW(TAG, "GPIO %d is not set for output", expander->first + gpio);
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return ESP_ERR_INVALID_ARG;
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}
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if (direct) {
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xSemaphoreTake(expander->mutex, pdMS_TO_TICKS(portMAX_DELAY));
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level = level ? mask : 0;
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mask &= expander->shadow;
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// only write if shadow not up to date
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if ((mask ^ level) && expander->model->write) {
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expander->shadow = (expander->shadow & ~(mask | level)) | level;
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expander->model->write(expander);
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}
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xSemaphoreGive(expander->mutex);
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ESP_LOGD(TAG, "Set level %x for GPIO %u => wrote %x", level, expander->first + gpio, expander->shadow);
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} else {
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queue_request_t request = { .gpio = gpio, .level = level, .type = ASYNC_WRITE, .expander = expander };
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if (xQueueSend(message_queue, &request, 0) == pdFALSE) return ESP_ERR_INVALID_RESPONSE;
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// notify service task that will write it when it can
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xTaskNotify(service_task, GPIO_EXP_WRITE, eSetValueWithoutOverwrite);
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}
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return ESP_OK;
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}
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/******************************************************************************
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* Set GPIO pullmode
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*/
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esp_err_t gpio_exp_set_pull_mode(int gpio, gpio_pull_mode_t mode, gpio_exp_t *expander) {
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if (gpio < GPIO_NUM_MAX && !expander) return gpio_set_pull_mode(gpio, mode);
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if ((expander = find_expander(expander, &gpio)) != NULL && expander->model->set_pull_mode) {
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expander->pullup &= ~(1 << gpio);
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expander->pulldown &= ~(1 << gpio);
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if (mode == GPIO_PULLUP_ONLY || mode == GPIO_PULLUP_PULLDOWN) expander->pullup |= 1 << gpio;
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if (mode == GPIO_PULLDOWN_ONLY || mode == GPIO_PULLUP_PULLDOWN) expander->pulldown |= 1 << gpio;
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expander->model->set_pull_mode(expander);
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return ESP_OK;
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}
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return ESP_ERR_INVALID_ARG;
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}
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/******************************************************************************
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* Wrapper function
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*/
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esp_err_t gpio_set_pull_mode_x(int gpio, gpio_pull_mode_t mode) {
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if (gpio < GPIO_NUM_MAX) return gpio_set_pull_mode(gpio, mode);
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return gpio_exp_set_pull_mode(gpio, mode, NULL);
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}
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esp_err_t gpio_set_direction_x(int gpio, gpio_mode_t mode) {
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if (gpio < GPIO_NUM_MAX) return gpio_set_direction(gpio, mode);
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return gpio_exp_set_direction(gpio, mode, NULL);
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}
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int gpio_get_level_x(int gpio) {
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if (gpio < GPIO_NUM_MAX) return gpio_get_level(gpio);
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return gpio_exp_get_level(gpio, 10, NULL);
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}
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esp_err_t gpio_set_level_x(int gpio, int level) {
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if (gpio < GPIO_NUM_MAX) return gpio_set_level(gpio, level);
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return gpio_exp_set_level(gpio, level, false, NULL);
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}
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esp_err_t gpio_isr_handler_add_x(int gpio, gpio_isr_t isr_handler, void* args) {
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if (gpio < GPIO_NUM_MAX) return gpio_isr_handler_add(gpio, isr_handler, args);
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return gpio_exp_isr_handler_add(gpio, isr_handler, 0, args, NULL);
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}
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esp_err_t gpio_isr_handler_remove_x(int gpio) {
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if (gpio < GPIO_NUM_MAX) return gpio_isr_handler_remove(gpio);
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return gpio_exp_isr_handler_remove(gpio, NULL);
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}
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/****************************************************************************************
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* INTR low-level handler
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*/
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static void IRAM_ATTR intr_isr_handler(void* arg) {
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gpio_exp_t *self = (gpio_exp_t*) arg;
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BaseType_t woken = pdFALSE;
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// edge interrupts do not work because of read/clear = potential short pulse
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gpio_intr_disable(self->intr);
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// activate all, including ourselves
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for (int i = 0; i < n_expanders; i++) if (expanders[i].intr == self->intr) expanders[i].intr_pending = true;
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xTaskNotifyFromISR(service_task, GPIO_EXP_INTR, eSetValueWithOverwrite, &woken);
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if (woken) portYIELD_FROM_ISR();
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ESP_EARLY_LOGD(TAG, "INTR for expander base %d", gpio_exp_get_base(self));
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}
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/****************************************************************************************
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* INTR debounce handler
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*/
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static void debounce_handler( TimerHandle_t xTimer ) {
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struct gpio_exp_isr_s *isr = (struct gpio_exp_isr_s*) pvTimerGetTimerID (xTimer);
|
|
isr->handler(isr->arg);
|
|
}
|
|
|
|
/****************************************************************************************
|
|
* Service task
|
|
*/
|
|
void service_handler(void *arg) {
|
|
while (1) {
|
|
queue_request_t request;
|
|
uint32_t notif = ulTaskNotifyTake(pdTRUE, portMAX_DELAY);
|
|
|
|
// we have been notified of an interrupt
|
|
if (notif == GPIO_EXP_INTR) {
|
|
/* If we want a smarter bitmap of expanders with a pending interrupt
|
|
we'll have to disable interrupts while clearing that bitmap. For
|
|
now, a loop will do */
|
|
for (int i = 0; i < n_expanders; i++) {
|
|
gpio_exp_t *expander = expanders + i;
|
|
|
|
// no interrupt for that gpio or not pending (safe as interrupt is disabled)
|
|
if (expander->intr < 0 || !expander->intr_pending) continue;
|
|
|
|
xSemaphoreTake(expander->mutex, pdMS_TO_TICKS(50));
|
|
|
|
// read GPIOs and clear all pending status
|
|
uint32_t value = expander->model->read(expander);
|
|
expander->age = xTaskGetTickCount();
|
|
|
|
// re-enable interrupt now that it has been cleared
|
|
expander->intr_pending = false;
|
|
gpio_intr_enable(expander->intr);
|
|
|
|
uint32_t pending = expander->pending | ((expander->shadow ^ value) & expander->r_mask);
|
|
expander->shadow = value;
|
|
expander->pending = 0;
|
|
|
|
xSemaphoreGive(expander->mutex);
|
|
ESP_LOGD(TAG, "Handling GPIO %d reads 0x%04x and has 0x%04x pending", expander->first, expander->shadow, pending);
|
|
|
|
for (int gpio = 31, clz = 0; pending && clz < 31; pending <<= (clz + 1)) {
|
|
clz = __builtin_clz(pending);
|
|
gpio -= clz;
|
|
if (expander->isr[gpio].timer) xTimerReset(expander->isr[gpio].timer, 1); // todo 0
|
|
else if (expander->isr[gpio].handler) expander->isr[gpio].handler(expander->isr[gpio].arg);
|
|
}
|
|
}
|
|
}
|
|
|
|
// check if we have some other pending requests
|
|
while (xQueueReceive(message_queue, &request, 0) == pdTRUE) {
|
|
esp_err_t err = gpio_exp_set_level(request.gpio, request.level, true, request.expander);
|
|
if (err != ESP_OK) ESP_LOGW(TAG, "Can't execute async GPIO %d write request (%d)", request.gpio, err);
|
|
}
|
|
}
|
|
}
|
|
|
|
/****************************************************************************************
|
|
* Find the expander related to base
|
|
*/
|
|
static gpio_exp_t* find_expander(gpio_exp_t *expander, int *gpio) {
|
|
// a mutex would be better, but risk is so small...
|
|
for (int i = 0; !expander && i < n_expanders; i++) {
|
|
if (*gpio >= expanders[i].first && *gpio <= expanders[i].last) expander = expanders + i;
|
|
}
|
|
|
|
// normalize GPIO number
|
|
if (expander && *gpio >= expander->first) *gpio -= expander->first;
|
|
|
|
return expander;
|
|
}
|
|
|
|
/****************************************************************************************
|
|
DRIVERS
|
|
****************************************************************************************/
|
|
|
|
/****************************************************************************************
|
|
* MPR121 family : init, direction, read and write
|
|
*/
|
|
static esp_err_t mpr121_init(gpio_exp_t* self) {
|
|
// soft reset the MPR121
|
|
esp_err_t err = i2c_write(self->phy.port, self->phy.addr, 0x80, 0x63, 1);
|
|
|
|
/*
|
|
There is variance of default values between libraries:
|
|
Reg AN3944 Adafruit_MPR121 BareConductive/MPR121
|
|
MHDR 0x2b 0x01 0x01 0x01
|
|
NHDR 0x2c 0x01 0x01 0x01
|
|
NCLR 0x2d 0x00 0x0e 0x10
|
|
FDLR 0x2e 0x00 0x00 0x20
|
|
|
|
MHDF 0x2f 0x01 0x01 0x01
|
|
NHDF 0x30 0x01 0x05 0x01
|
|
NCLF 0x31 0xff 0x01 0x10
|
|
FDLF 0x32 0x20 0x00 0x20
|
|
|
|
NHDT 0x33 ---- 0x00 0x01
|
|
NCLT 0x34 ---- 0x00 0x10
|
|
FDLT 0x35 ---- 0x00 0xff
|
|
|
|
DTR 0x5b ---- 0x00 0x11
|
|
AFE1 0x5c ---- 0x10 0xff
|
|
AFE2 0x5d 0x04 0x20 0x30
|
|
ECR 0x5e 0x0c ---- 0xcc
|
|
|
|
ACCR0 0x7b 0x0b 0x0b 0x00
|
|
ACCR1 0x7c ---- ---- 0x00
|
|
USL 0x7d 0x9c 0xc8 0x00
|
|
LSL 0x7e 0x65 0xb4 0x00
|
|
TL 0x7f 0x8c 0x82 0x00
|
|
|
|
BareConductive MPR121 values used below.
|
|
*/
|
|
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x2b, 0x01, 1); // MHDR
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x2c, 0x01, 1); // NHDR
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x2d, 0x10, 1); // NCLR
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x2e, 0x20, 1); // FDLR
|
|
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x2f, 0x01, 1); // MHDF
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x30, 0x01, 1); // NHDF
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x31, 0x10, 1); // NCLF
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x32, 0x20, 1); // FDLF
|
|
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x33, 0x01, 1); // NHDT
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x34, 0x10, 1); // NCLT
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x35, 0xff, 1); // FDLT
|
|
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x5b, 0x11, 1); // DTR
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x5c, 0xff, 1); // AFE1
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x5d, 0x30, 1); // AFE2
|
|
// ECR set last
|
|
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x7b, 0x00, 1); // ACCR0
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x7c, 0x00, 1); // ACCR1
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x7d, 0x00, 1); // USL
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x7e, 0x00, 1); // LSL
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x7f, 0x00, 1); // TL
|
|
|
|
|
|
// Touch & Release thresholds
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x41, 0x28, 1); // ELE0 Touch Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x42, 0x14, 1); // ELE0 Release Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x43, 0x28, 1); // ELE1 Touch Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x44, 0x14, 1); // ELE1 Release Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x45, 0x28, 1); // ELE2 Touch Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x46, 0x14, 1); // ELE2 Release Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x47, 0x28, 1); // ELE3 Touch Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x48, 0x14, 1); // ELE3 Release Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x49, 0x28, 1); // ELE4 Touch Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x4a, 0x14, 1); // ELE4 Release Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x4b, 0x28, 1); // ELE5 Touch Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x4c, 0x14, 1); // ELE5 Release Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x4d, 0x28, 1); // ELE6 Touch Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x4e, 0x14, 1); // ELE6 Release Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x4f, 0x28, 1); // ELE7 Touch Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x50, 0x14, 1); // ELE7 Release Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x51, 0x28, 1); // ELE8 Touch Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x52, 0x14, 1); // ELE8 Release Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x53, 0x28, 1); // ELE9 Touch Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x54, 0x14, 1); // ELE9 Release Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x55, 0x28, 1); // ELE10 Touch Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x56, 0x14, 1); // ELE10 Release Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x57, 0x28, 1); // ELE11 Touch Threshold
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x58, 0x14, 1); // ELE11 Release Threshold
|
|
|
|
// finally set to run mode with 12 electrodes enabled
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x5e, 0xcc, 1); // ECR
|
|
|
|
return err;
|
|
}
|
|
|
|
static uint32_t mpr121_read(gpio_exp_t* self) {
|
|
// only return the lower 12 bits of the pin status registers
|
|
return i2c_read(self->phy.port, self->phy.addr, 0x00, 2) & 0x0fff;
|
|
}
|
|
|
|
static void mpr121_write(gpio_exp_t* self) {
|
|
ESP_LOGE(TAG, "MPR121 GPIO write not implemented");
|
|
}
|
|
|
|
/****************************************************************************************
|
|
* PCA9535 family : direction, read and write
|
|
*/
|
|
static void pca9535_set_direction(gpio_exp_t* self) {
|
|
i2c_write(self->phy.port, self->phy.addr, 0x06, self->r_mask, 2);
|
|
}
|
|
|
|
static uint32_t pca9535_read(gpio_exp_t* self) {
|
|
return i2c_read(self->phy.port, self->phy.addr, 0x00, 2);
|
|
}
|
|
|
|
static void pca9535_write(gpio_exp_t* self) {
|
|
i2c_write(self->phy.port, self->phy.addr, 0x02, self->shadow, 2);
|
|
}
|
|
|
|
/****************************************************************************************
|
|
* PCA85xx family : read and write
|
|
*/
|
|
static uint32_t pca85xx_read(gpio_exp_t* self) {
|
|
// must return the full set of pins, not just inputs
|
|
uint32_t data = i2c_read(self->phy.port, self->phy.addr, 0xff, 2);
|
|
return (data & self->r_mask) | (self->shadow & ~self->r_mask);
|
|
}
|
|
|
|
static void pca85xx_write(gpio_exp_t* self) {
|
|
/*
|
|
There is no good option with this chip: normally, unused pin should be set to input
|
|
to avoid any conflict but then they float and create tons of suprious. So option 1 is
|
|
to le tthem float and option 2 is to set them as output to 0.
|
|
In addition, setting an output pin to 1 equals is making it an input and if this is
|
|
use to short a led (e.g.) instead of being the sink, the it generates a spurious
|
|
*/
|
|
// option 1
|
|
// i2c_write(self->phy.port, self->phy.addr, 0xff, (self->shadow & self->w_mask) | ~self->w_mask, 2);
|
|
// option 2
|
|
i2c_write(self->phy.port, self->phy.addr, 0xff, (self->shadow & self->w_mask) | self->r_mask, 2);
|
|
}
|
|
|
|
/****************************************************************************************
|
|
* MCP23017 family : init, direction, read and write
|
|
*/
|
|
static esp_err_t mcp23017_init(gpio_exp_t* self) {
|
|
/*
|
|
0111 x10x = same bank, mirrot single int, no sequentµial, open drain, active low
|
|
not sure about this funny change of mapping of the control register itself, really?
|
|
*/
|
|
esp_err_t err = i2c_write(self->phy.port, self->phy.addr, 0x05, 0x74, 1);
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x0a, 0x74, 1);
|
|
|
|
// no interrupt on comparison or on change
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x04, 0x00, 2);
|
|
err |= i2c_write(self->phy.port, self->phy.addr, 0x08, 0x00, 2);
|
|
|
|
return err;
|
|
}
|
|
|
|
static void mcp23017_set_direction(gpio_exp_t* self) {
|
|
// default to input and set real input to generate interrupt
|
|
i2c_write(self->phy.port, self->phy.addr, 0x00, ~self->w_mask, 2);
|
|
i2c_write(self->phy.port, self->phy.addr, 0x04, self->r_mask, 2);
|
|
}
|
|
|
|
static void mcp23017_set_pull_mode(gpio_exp_t* self) {
|
|
i2c_write(self->phy.port, self->phy.addr, 0x0c, self->pullup, 2);
|
|
}
|
|
|
|
static uint32_t mcp23017_read(gpio_exp_t* self) {
|
|
// read the pins value, not the stored one @interrupt
|
|
return i2c_read(self->phy.port, self->phy.addr, 0x12, 2);
|
|
}
|
|
|
|
static void mcp23017_write(gpio_exp_t* self) {
|
|
i2c_write(self->phy.port, self->phy.addr, 0x12, self->shadow, 2);
|
|
}
|
|
|
|
/****************************************************************************************
|
|
* MCP23s17 family : init, direction, read and write
|
|
*/
|
|
static esp_err_t mcp23s17_init(gpio_exp_t* self) {
|
|
if ((self->spi_handle = spi_config(&self->phy)) == NULL) return ESP_ERR_INVALID_ARG;
|
|
|
|
/*
|
|
0111 x10x = same bank, mirrot single int, no sequentµial, open drain, active low
|
|
not sure about this funny change of mapping of the control register itself, really?
|
|
*/
|
|
esp_err_t err = spi_write(self->spi_handle, self->phy.addr, 0x05, 0x74, 1);
|
|
err |= spi_write(self->spi_handle, self->phy.addr, 0x0a, 0x74, 1);
|
|
|
|
// no interrupt on comparison or on change
|
|
err |= spi_write(self->spi_handle, self->phy.addr, 0x04, 0x00, 2);
|
|
err |= spi_write(self->spi_handle, self->phy.addr, 0x08, 0x00, 2);
|
|
|
|
return err;
|
|
}
|
|
|
|
static void mcp23s17_set_direction(gpio_exp_t* self) {
|
|
// default to input and set real input to generate interrupt
|
|
spi_write(self->spi_handle, self->phy.addr, 0x00, ~self->w_mask, 2);
|
|
spi_write(self->spi_handle, self->phy.addr, 0x04, self->r_mask, 2);
|
|
}
|
|
|
|
static void mcp23s17_set_pull_mode(gpio_exp_t* self) {
|
|
spi_write(self->spi_handle, self->phy.addr, 0x0c, self->pullup, 2);
|
|
}
|
|
|
|
static uint32_t mcp23s17_read(gpio_exp_t* self) {
|
|
// read the pins value, not the stored one @interrupt
|
|
return spi_read(self->spi_handle, self->phy.addr, 0x12, 2);
|
|
}
|
|
|
|
static void mcp23s17_write(gpio_exp_t* self) {
|
|
spi_write(self->spi_handle, self->phy.addr, 0x12, self->shadow, 2);
|
|
}
|
|
|
|
/***************************************************************************************
|
|
I2C low level
|
|
***************************************************************************************/
|
|
|
|
/****************************************************************************************
|
|
* I2C write up to 32 bits
|
|
*/
|
|
static esp_err_t i2c_write(uint8_t port, uint8_t addr, uint8_t reg, uint32_t data, int len) {
|
|
i2c_cmd_handle_t cmd = i2c_cmd_link_create();
|
|
i2c_master_start(cmd);
|
|
|
|
i2c_master_write_byte(cmd, (addr << 1) | I2C_MASTER_WRITE, I2C_MASTER_NACK);
|
|
if (reg != 0xff) i2c_master_write_byte(cmd, reg, I2C_MASTER_NACK);
|
|
|
|
// works with our endianness
|
|
if (len > 1) i2c_master_write(cmd, (uint8_t*) &data, len, I2C_MASTER_NACK);
|
|
else i2c_master_write_byte(cmd, data, I2C_MASTER_NACK);
|
|
|
|
i2c_master_stop(cmd);
|
|
esp_err_t ret = i2c_master_cmd_begin(port, cmd, 100 / portTICK_RATE_MS);
|
|
i2c_cmd_link_delete(cmd);
|
|
|
|
if (ret != ESP_OK) {
|
|
ESP_LOGW(TAG, "I2C write failed");
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/****************************************************************************************
|
|
* I2C read up to 32 bits
|
|
*/
|
|
static uint32_t i2c_read(uint8_t port, uint8_t addr, uint8_t reg, int len) {
|
|
uint32_t data = 0;
|
|
|
|
i2c_cmd_handle_t cmd = i2c_cmd_link_create();
|
|
|
|
i2c_master_start(cmd);
|
|
|
|
// when using a register, write it's value then the device address again
|
|
if (reg != 0xff) {
|
|
i2c_master_write_byte(cmd, (addr << 1) | I2C_MASTER_WRITE, I2C_MASTER_NACK);
|
|
i2c_master_write_byte(cmd, reg, I2C_MASTER_NACK);
|
|
i2c_master_start(cmd);
|
|
i2c_master_write_byte(cmd, (addr << 1) | I2C_MASTER_READ, I2C_MASTER_NACK);
|
|
} else {
|
|
i2c_master_write_byte(cmd, (addr << 1) | I2C_MASTER_READ, I2C_MASTER_NACK);
|
|
}
|
|
|
|
// works with our endianness
|
|
if (len > 1) i2c_master_read(cmd, (uint8_t*) &data, len, I2C_MASTER_LAST_NACK);
|
|
else i2c_master_read_byte(cmd, (uint8_t*) &data, I2C_MASTER_NACK);
|
|
|
|
i2c_master_stop(cmd);
|
|
esp_err_t ret = i2c_master_cmd_begin(port, cmd, 100 / portTICK_RATE_MS);
|
|
i2c_cmd_link_delete(cmd);
|
|
|
|
if (ret != ESP_OK) {
|
|
ESP_LOGW(TAG, "I2C read failed");
|
|
}
|
|
|
|
return data;
|
|
}
|
|
|
|
/***************************************************************************************
|
|
SPI low level
|
|
***************************************************************************************/
|
|
|
|
/****************************************************************************************
|
|
* SPI device addition
|
|
*/
|
|
static spi_device_handle_t spi_config(struct gpio_exp_phy_s *phy) {
|
|
spi_device_interface_config_t config = { };
|
|
spi_device_handle_t handle = NULL;
|
|
|
|
config.command_bits = config.address_bits = 8;
|
|
config.clock_speed_hz = phy->speed ? phy->speed : SPI_MASTER_FREQ_8M;
|
|
config.spics_io_num = phy->cs_pin;
|
|
config.queue_size = 1;
|
|
config.flags = SPI_DEVICE_NO_DUMMY;
|
|
|
|
spi_bus_add_device( phy->host, &config, &handle );
|
|
ESP_LOGI(TAG, "SPI expander initialized on host:%d with cs:%d and speed:%dHz", phy->host, phy->cs_pin, config.clock_speed_hz);
|
|
|
|
return handle;
|
|
}
|
|
|
|
/****************************************************************************************
|
|
* SPI write up to 32 bits
|
|
*/
|
|
static esp_err_t spi_write(spi_device_handle_t handle, uint8_t addr, uint8_t reg, uint32_t data, int len) {
|
|
spi_transaction_t transaction = { };
|
|
|
|
// rx_buffer is NULL, nothing to receive
|
|
transaction.flags = SPI_TRANS_USE_TXDATA;
|
|
transaction.cmd = addr << 1;
|
|
transaction.addr = reg;
|
|
transaction.tx_data[0] = data; transaction.tx_data[1] = data >> 8;
|
|
transaction.length = len * 8;
|
|
|
|
// only do polling as we don't have contention on SPI (otherwise DMA for transfers > 16 bytes)
|
|
return spi_device_polling_transmit(handle, &transaction);
|
|
}
|
|
|
|
/****************************************************************************************
|
|
* SPI read up to 32 bits
|
|
*/
|
|
static uint32_t spi_read(spi_device_handle_t handle, uint8_t addr, uint8_t reg, int len) {
|
|
spi_transaction_t *transaction = heap_caps_calloc(1, sizeof(spi_transaction_t), MALLOC_CAP_DMA);
|
|
|
|
// tx_buffer is NULL, nothing to transmit except cmd/addr
|
|
transaction->flags = SPI_TRANS_USE_RXDATA;
|
|
transaction->cmd = (addr << 1) | 0x01;
|
|
transaction->addr = reg;
|
|
transaction->length = len * 8;
|
|
|
|
// only do polling as we don't have contention on SPI (otherwise DMA for transfers > 16 bytes)
|
|
spi_device_polling_transmit(handle, transaction);
|
|
uint32_t data = *(uint32_t*) transaction->rx_data;
|
|
free(transaction);
|
|
|
|
return data;
|
|
} |