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compatibitly mit esp-idf pure

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jomjol
2020-11-20 19:34:55 +01:00
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16
code/components/esp32-camera-master/sensors/private_include/nt99141.h Normal file
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/*
* This file is part of the OpenMV project.
* Copyright (c) 2013/2014 Ibrahim Abdelkader <i.abdalkader@gmail.com>
* This work is licensed under the MIT license, see the file LICENSE for details.
*
* NT99141 driver.
*
*/
#ifndef __NT99141_H__
#define __NT99141_H__
#include "sensor.h"
int NT99141_init(sensor_t *sensor);
#endif // __NT99141_H__

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code/components/esp32-camera-master/sensors/private_include/nt99141_regs.h Normal file
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/*
* NT99141 register definitions.
*/
#ifndef __NT99141_REG_REGS_H__
#define __NT99141_REG_REGS_H__
/* system control registers */
#define SYSTEM_CTROL0 0x3021 // Bit[7]: Software reset
// Bit[6]: Software power down
// Bit[5]: Reserved
// Bit[4]: SRB clock SYNC enable
// Bit[3]: Isolation suspend select
// Bit[2:0]: Not used
/* output format control registers */
#define FORMAT_CTRL 0x501F // Format select
// Bit[2:0]:
// 000: YUV422
// 001: RGB
// 010: Dither
// 011: RAW after DPC
// 101: RAW after CIP
/* format control registers */
#define FORMAT_CTRL00 0x4300
/* frame control registers */
#define FRAME_CTRL01 0x4201 // Control Passed Frame Number When both ON and OFF number set to 0x00,frame control is in bypass mode
// Bit[7:4]: Not used
// Bit[3:0]: Frame ON number
#define FRAME_CTRL02 0x4202 // Control Masked Frame Number When both ON and OFF number set to 0x00,frame control is in bypass mode
// Bit[7:4]: Not used
// BIT[3:0]: Frame OFF number
/* ISP top control registers */
#define PRE_ISP_TEST_SETTING_1 0x3025 // Bit[7]: Test enable
// 0: Test disable
// 1: Color bar enable
// Bit[6]: Rolling
// Bit[5]: Transparent
// Bit[4]: Square black and white
// Bit[3:2]: Color bar style
// 00: Standard 8 color bar
// 01: Gradual change at vertical mode 1
// 10: Gradual change at horizontal
// 11: Gradual change at vertical mode 2
// Bit[1:0]: Test select
// 00: Color bar
// 01: Random data
// 10: Square data
// 11: Black image
//exposure = {0x3500[3:0], 0x3501[7:0], 0x3502[7:0]} / 16 × tROW
/* AEC/AGC control functions */
#define AEC_PK_MANUAL 0x3201 // AEC Manual Mode Control
// Bit[7:6]: Reserved
// Bit[5]: Gain delay option
// Valid when 0x3503[4]=1’b0
// 0: Delay one frame latch
// 1: One frame latch
// Bit[4:2]: Reserved
// Bit[1]: AGC manual
// 0: Auto enable
// 1: Manual enable
// Bit[0]: AEC manual
// 0: Auto enable
// 1: Manual enable
//gain = {0x350A[1:0], 0x350B[7:0]} / 16
/* mirror and flip registers */
#define TIMING_TC_REG20 0x3022 // Timing Control Register
// Bit[2:1]: Vertical flip enable
// 00: Normal
// 11: Vertical flip
// Bit[0]: Vertical binning enable
#define TIMING_TC_REG21 0x3022 // Timing Control Register
// Bit[5]: Compression Enable
// Bit[2:1]: Horizontal mirror enable
// 00: Normal
// 11: Horizontal mirror
// Bit[0]: Horizontal binning enable
#define CLOCK_POL_CONTROL 0x3024// Bit[5]: PCLK polarity 0: active low
// 1: active high
// Bit[3]: Gate PCLK under VSYNC
// Bit[2]: Gate PCLK under HREF
// Bit[1]: HREF polarity
// 0: active low
// 1: active high
// Bit[0] VSYNC polarity
// 0: active low
// 1: active high
#define DRIVE_CAPABILITY 0x306a // Bit[7:6]:
// 00: 1x
// 01: 2x
// 10: 3x
// 11: 4x
#define X_ADDR_ST_H 0x3800 //Bit[3:0]: X address start[11:8]
#define X_ADDR_ST_L 0x3801 //Bit[7:0]: X address start[7:0]
#define Y_ADDR_ST_H 0x3802 //Bit[2:0]: Y address start[10:8]
#define Y_ADDR_ST_L 0x3803 //Bit[7:0]: Y address start[7:0]
#define X_ADDR_END_H 0x3804 //Bit[3:0]: X address end[11:8]
#define X_ADDR_END_L 0x3805 //Bit[7:0]:
#define Y_ADDR_END_H 0x3806 //Bit[2:0]: Y address end[10:8]
#define Y_ADDR_END_L 0x3807 //Bit[7:0]:
// Size after scaling
#define X_OUTPUT_SIZE_H 0x3808 //Bit[3:0]: DVP output horizontal width[11:8]
#define X_OUTPUT_SIZE_L 0x3809 //Bit[7:0]:
#define Y_OUTPUT_SIZE_H 0x380a //Bit[2:0]: DVP output vertical height[10:8]
#define Y_OUTPUT_SIZE_L 0x380b //Bit[7:0]:
#define X_TOTAL_SIZE_H 0x380c //Bit[3:0]: Total horizontal size[11:8]
#define X_TOTAL_SIZE_L 0x380d //Bit[7:0]:
#define Y_TOTAL_SIZE_H 0x380e //Bit[7:0]: Total vertical size[15:8]
#define Y_TOTAL_SIZE_L 0x380f //Bit[7:0]:
#define X_OFFSET_H 0x3810 //Bit[3:0]: ISP horizontal offset[11:8]
#define X_OFFSET_L 0x3811 //Bit[7:0]:
#define Y_OFFSET_H 0x3812 //Bit[2:0]: ISP vertical offset[10:8]
#define Y_OFFSET_L 0x3813 //Bit[7:0]:
#define X_INCREMENT 0x3814 //Bit[7:4]: Horizontal odd subsample increment
//Bit[3:0]: Horizontal even subsample increment
#define Y_INCREMENT 0x3815 //Bit[7:4]: Vertical odd subsample increment
//Bit[3:0]: Vertical even subsample increment
// Size before scaling
//#define X_INPUT_SIZE (X_ADDR_END - X_ADDR_ST + 1 - (2 * X_OFFSET))
//#define Y_INPUT_SIZE (Y_ADDR_END - Y_ADDR_ST + 1 - (2 * Y_OFFSET))
#define ISP_CONTROL_01 0x3021 // Bit[5]: Scale enable
// 0: Disable
// 1: Enable
#define SCALE_CTRL_1 0x5601 // Bit[6:4]: HDIV RW
// DCW scale times
// 000: DCW 1 time
// 001: DCW 2 times
// 010: DCW 4 times
// 100: DCW 8 times
// 101: DCW 16 times
// Others: DCW 16 times
// Bit[2:0]: VDIV RW
// DCW scale times
// 000: DCW 1 time
// 001: DCW 2 times
// 010: DCW 4 times
// 100: DCW 8 times
// 101: DCW 16 times
// Others: DCW 16 times
#define SCALE_CTRL_2 0x5602 // X_SCALE High Bits
#define SCALE_CTRL_3 0x5603 // X_SCALE Low Bits
#define SCALE_CTRL_4 0x5604 // Y_SCALE High Bits
#define SCALE_CTRL_5 0x5605 // Y_SCALE Low Bits
#define SCALE_CTRL_6 0x5606 // Bit[3:0]: V Offset
#define PCLK_RATIO 0x3824 // Bit[4:0]: PCLK ratio manual
#define VFIFO_CTRL0C 0x460C // Bit[1]: PCLK manual enable
// 0: Auto
// 1: Manual by PCLK_RATIO
#define VFIFO_X_SIZE_H 0x4602
#define VFIFO_X_SIZE_L 0x4603
#define VFIFO_Y_SIZE_H 0x4604
#define VFIFO_Y_SIZE_L 0x4605
#define SC_PLLS_CTRL0 0x303a // Bit[7]: PLLS bypass
#define SC_PLLS_CTRL1 0x303b // Bit[4:0]: PLLS multiplier
#define SC_PLLS_CTRL2 0x303c // Bit[6:4]: PLLS charge pump control
// Bit[3:0]: PLLS system divider
#define SC_PLLS_CTRL3 0x303d // Bit[5:4]: PLLS pre-divider
// 00: 1
// 01: 1.5
// 10: 2
// 11: 3
// Bit[2]: PLLS root-divider - 1
// Bit[1:0]: PLLS seld5
// 00: 1
// 01: 1
// 10: 2
// 11: 2.5
#define COMPRESSION_CTRL00 0x4400 //
#define COMPRESSION_CTRL01 0x4401 //
#define COMPRESSION_CTRL02 0x4402 //
#define COMPRESSION_CTRL03 0x4403 //
#define COMPRESSION_CTRL04 0x4404 //
#define COMPRESSION_CTRL05 0x4405 //
#define COMPRESSION_CTRL06 0x4406 //
#define COMPRESSION_CTRL07 0x3401 // Bit[5:0]: QS
#define COMPRESSION_ISI_CTRL 0x4408 //
#define COMPRESSION_CTRL09 0x4409 //
#define COMPRESSION_CTRL0a 0x440a //
#define COMPRESSION_CTRL0b 0x440b //
#define COMPRESSION_CTRL0c 0x440c //
#define COMPRESSION_CTRL0d 0x440d //
#define COMPRESSION_CTRL0E 0x440e //
/**
* @brief register value
*/
#define TEST_COLOR_BAR 0x02 /* Enable Color Bar roling Test */
#define AEC_PK_MANUAL_AGC_MANUALEN 0x02 /* Enable AGC Manual enable */
#define AEC_PK_MANUAL_AEC_MANUALEN 0x01 /* Enable AEC Manual enable */
#define TIMING_TC_REG20_VFLIP 0x01 /* Vertical flip enable */
#define TIMING_TC_REG21_HMIRROR 0x02 /* Horizontal mirror enable */
#endif // __NT99141_REG_REGS_H__

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code/components/esp32-camera-master/sensors/private_include/nt99141_settings.h Normal file
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#ifndef _NT99141_SETTINGS_H_
#define _NT99141_SETTINGS_H_
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "nt99141_regs.h"
static const ratio_settings_t ratio_table[] = {
// mw, mh, sx, sy, ex, ey, ox, oy, tx, ty
{ 1280, 720, 0, 4, 1283, 723, 0, 4, 1660, 963 },
};
#define REG_DLY 0xffff
#define REGLIST_TAIL 0x0000
static const DRAM_ATTR uint16_t sensor_default_regs[][2] = {
//initial
{0x3021, 0x00},
{REG_DLY, 100}, // delay 100ms
{0x3109, 0x04},
{0x3040, 0x04},
{0x3041, 0x02},
{0x3042, 0xFF},
{0x3043, 0x08},
{0x3052, 0xE0},
{0x305F, 0x33},
{0x3100, 0x07},
{0x3106, 0x03},
{0x3105, 0x01},
{0x3108, 0x05},
{0x3110, 0x22},
{0x3111, 0x57},
{0x3112, 0x22},
{0x3113, 0x55},
{0x3114, 0x05},
{0x3135, 0x00},
{0x32F0, 0x01},
{0x3290, 0x01},
{0x3291, 0x80},
{0x3296, 0x01},
{0x3297, 0x73},
{0x3250, 0x80},
{0x3251, 0x03},
{0x3252, 0xFF},
{0x3253, 0x00},
{0x3254, 0x03},
{0x3255, 0xFF},
{0x3256, 0x00},
{0x3257, 0x50},
{0x3270, 0x00},
{0x3271, 0x0C},
{0x3272, 0x18},
{0x3273, 0x32},
{0x3274, 0x44},
{0x3275, 0x54},
{0x3276, 0x70},
{0x3277, 0x88},
{0x3278, 0x9D},
{0x3279, 0xB0},
{0x327A, 0xCF},
{0x327B, 0xE2},
{0x327C, 0xEF},
{0x327D, 0xF7},
{0x327E, 0xFF},
{0x3302, 0x00},
{0x3303, 0x40},
{0x3304, 0x00},
{0x3305, 0x96},
{0x3306, 0x00},
{0x3307, 0x29},
{0x3308, 0x07},
{0x3309, 0xBA},
{0x330A, 0x06},
{0x330B, 0xF5},
{0x330C, 0x01},
{0x330D, 0x51},
{0x330E, 0x01},
{0x330F, 0x30},
{0x3310, 0x07},
{0x3311, 0x16},
{0x3312, 0x07},
{0x3313, 0xBA},
{0x3326, 0x02},
{0x32F6, 0x0F},
{0x32F9, 0x42},
{0x32FA, 0x24},
{0x3325, 0x4A},
{0x3330, 0x00},
{0x3331, 0x0A},
{0x3332, 0xFF},
{0x3338, 0x30},
{0x3339, 0x84},
{0x333A, 0x48},
{0x333F, 0x07},
{0x3360, 0x10},
{0x3361, 0x18},
{0x3362, 0x1f},
{0x3363, 0x37},
{0x3364, 0x80},
{0x3365, 0x80},
{0x3366, 0x68},
{0x3367, 0x60},
{0x3368, 0x30},
{0x3369, 0x28},
{0x336A, 0x20},
{0x336B, 0x10},
{0x336C, 0x00},
{0x336D, 0x20},
{0x336E, 0x1C},
{0x336F, 0x18},
{0x3370, 0x10},
{0x3371, 0x38},
{0x3372, 0x3C},
{0x3373, 0x3F},
{0x3374, 0x3F},
{0x338A, 0x34},
{0x338B, 0x7F},
{0x338C, 0x10},
{0x338D, 0x23},
{0x338E, 0x7F},
{0x338F, 0x14},
{0x3375, 0x08},
{0x3376, 0x0C},
{0x3377, 0x18},
{0x3378, 0x20},
{0x3012, 0x02},
{0x3013, 0xD0},
{0x3025, 0x02}, //colorbar
{REGLIST_TAIL, 0x00}, // tail
};
static const DRAM_ATTR uint16_t sensor_fmt_jpeg[][2] = {
{0x32F0, 0x70}, // YUV422
{REGLIST_TAIL, 0x00}, // tail
};
static const DRAM_ATTR uint16_t sensor_fmt_raw[][2] = {
{0x32F0, 0x50}, // RAW
{REGLIST_TAIL, 0x00}, // tail
};
static const DRAM_ATTR uint16_t sensor_fmt_grayscale[][2] = {
{0x32F1, 0x01},
{REGLIST_TAIL, 0x00}, // tail
};
static const DRAM_ATTR uint16_t sensor_fmt_yuv422[][2] = {
{0x32F0, 0x00}, // YUV422
{REGLIST_TAIL, 0x00}, // tail
};
static const DRAM_ATTR uint16_t sensor_fmt_rgb565[][2] = {
{0x32F0, 0x01}, // RGB
{REGLIST_TAIL, 0x00}, // tail
};
static const DRAM_ATTR uint8_t sensor_saturation_levels[9][1] = {
{0x60},//-4
{0x68},//-3
{0x70},//-2
{0x78},//-1
{0x80},//0
{0x88},//+1
{0x90},//+2
{0x98},//+3
{0xA0},//+4
};
static const DRAM_ATTR uint8_t sensor_special_effects[7][4] = {
{0x00, 0x80, 0x80, 0x01},//Normal
{0x03, 0x80, 0x80, 0x01},//Negative
{0x01, 0x80, 0x80, 0x01},//Grayscale
{0x05, 0x2A, 0xF0, 0x01},//Red Tint
{0x05, 0x60, 0x20, 0x01},//Green Tint
{0x05, 0xF0, 0x80, 0x01},//Blue Tint
{0x02, 0x80, 0x80, 0x01},//Sepia
};
// AE LEVEL
static const DRAM_ATTR uint16_t sensor_ae_level[][2] = {
// 1. [AE_Target : 0x24]
// Set_Device_Format = FORMAT_16_8
// SET_Device_Addr = 0x54
{0x32B8, 0x29 },
{0x32B9, 0x1F },
{0x32BC, 0x24 },
{0x32BD, 0x27 },
{0x32BE, 0x21 },
//------------------------------------------------------------------------
// 2. [AE_Target : 0x28]
// Set_Device_Format = FORMAT_16_8
// SET_Device_Addr = 0x54
{0x32B8, 0x2D },
{0x32B9, 0x23 },
{0x32BC, 0x28 },
{0x32BD, 0x2B },
{0x32BE, 0x25 },
//------------------------------------------------------------------------
// 3. [AE_Target : 0x2C]
// Set_Device_Format = FORMAT_16_8
// SET_Device_Addr = 0x54
{0x32B8, 0x32 },
{0x32B9, 0x26 },
{0x32BC, 0x2C },
{0x32BD, 0x2F },
{0x32BE, 0x29 },
//------------------------------------------------------------------------
// 4, [AE_Target : 0x30]
// Set_Device_Format = FORMAT_16_8
// SET_Device_Addr = 0x54
{0x32B8, 0x36 },
{0x32B9, 0x2A },
{0x32BC, 0x30 },
{0x32BD, 0x33 },
{0x32BE, 0x2D },
//------------------------------------------------------------------------
// 5. [AE_Target : 0x34]
// Set_Device_Format = FORMAT_16_8
// SET_Device_Addr = 0x54
{0x32B8, 0x3B },
{0x32B9, 0x2D },
{0x32BC, 0x34 },
{0x32BD, 0x38 },
{0x32BE, 0x30 },
//------------------------------------------------------------------------
// 6. [AE_Target : 0x38]
// Set_Device_Format = FORMAT_16_8
// SET_Device_Addr = 0x54
{0x32B8, 0x3F },
{0x32B9, 0x31 },
{0x32BC, 0x38 },
{0x32BD, 0x3C },
{0x32BE, 0x34 },
//------------------------------------------------------------------------
// 7. [AE_Target : 0x3D]
// Set_Device_Format = FORMAT_16_8
// SET_Device_Addr = 0x54
{0x32B8, 0x44 },
{0x32B9, 0x34 },
{0x32BC, 0x3C },
{0x32BD, 0x40 },
{0x32BE, 0x38 },
//------------------------------------------------------------------------
// 8. [AE_Target : 0x40]
// Set_Device_Format = FORMAT_16_8
// SET_Device_Addr = 0x54
{0x32B8, 0x48 },
{0x32B9, 0x38 },
{0x32BC, 0x40 },
{0x32BD, 0x44 },
{0x32BE, 0x3C },
//------------------------------------------------------------------------
// 9. [AE_Target : 0x44]
// Set_Device_Format = FORMAT_16_8
// SET_Device_Addr = 0x54
{0x32B8, 0x4D },
{0x32B9, 0x3B },
{0x32BC, 0x44 },
{0x32BD, 0x49 },
{0x32BE, 0x3F },
};
static const DRAM_ATTR uint16_t sensor_framesize_HD[][2] = {
//[JPEG_1280x720_8.18_8.18_Fps]
{0x3021, 0x00},
{REG_DLY, 100}, // delay 100ms
{0x32BF, 0x60},
{0x32C0, 0x5A},
{0x32C1, 0x5A},
{0x32C2, 0x5A},
{0x32C3, 0x00},
{0x32C4, 0x20},
{0x32C5, 0x20},
{0x32C6, 0x20},
{0x32C7, 0x00},
{0x32C8, 0x3C},
{0x32C9, 0x5A},
{0x32CA, 0x7A},
{0x32CB, 0x7A},
{0x32CC, 0x7A},
{0x32CD, 0x7A},
{0x32DB, 0x5E},
{0x32F0, 0x70},
{0x3400, 0x08},
{0x3400, 0x00},
{0x3401, 0x4E},
{0x3404, 0x00},
{0x3405, 0x00},
{0x3410, 0x00},
{0x3200, 0x3E},
{0x3201, 0x0F},
{0x3028, 0x0F},
{0x3029, 0x00},
{0x302A, 0x08},
{0x3022, 0x24},
{0x3023, 0x24},
{0x3002, 0x00},
{0x3003, 0x04},
{0x3004, 0x00},
{0x3005, 0x04},
{0x3006, 0x05},
{0x3007, 0x03},
{0x3008, 0x02},
{0x3009, 0xD3},
{0x300A, 0x06},
{0x300B, 0x7C},
{0x300C, 0x02},
{0x300D, 0xE0},
{0x300E, 0x05},
{0x300F, 0x00},
{0x3010, 0x02},
{0x3011, 0xD0},
{0x32B8, 0x3F},
{0x32B9, 0x31},
{0x32BB, 0x87},
{0x32BC, 0x38},
{0x32BD, 0x3C},
{0x32BE, 0x34},
{0x3201, 0x3F},
{0x3021, 0x06},
{0x3025, 0x00}, //normal
{0x3400, 0x01},
{0x3060, 0x01},
{REGLIST_TAIL, 0x00}, // tail
};
static const DRAM_ATTR uint16_t sensor_framesize_VGA[][2] = {
//[JPEG_640x480_10.14_10.14_Fps]
{0x3021, 0x00},
{REG_DLY, 100}, // delay 100ms
{0x32BF, 0x60},
{0x32C0, 0x5A},
{0x32C1, 0x5A},
{0x32C2, 0x5A},
{0x32C3, 0x00},
{0x32C4, 0x20},
{0x32C5, 0x20},
{0x32C6, 0x20},
{0x32C7, 0x00},
{0x32C8, 0x4B},
{0x32C9, 0x5A},
{0x32CA, 0x7A},
{0x32CB, 0x7A},
{0x32CC, 0x7A},
{0x32CD, 0x7A},
{0x32DB, 0x62},
{0x32F0, 0x70},
{0x3400, 0x08},
{0x3400, 0x00},
{0x3401, 0x4E},
{0x3404, 0x00},
{0x3405, 0x00},
{0x3410, 0x00},
{0x32E0, 0x02},
{0x32E1, 0x80},
{0x32E2, 0x01},
{0x32E3, 0xE0},
{0x32E4, 0x00},
{0x32E5, 0x80},
{0x32E6, 0x00},
{0x32E7, 0x80},
{0x3200, 0x3E},
{0x3201, 0x0F},
{0x3028, 0x0F},
{0x3029, 0x00},
{0x302A, 0x08},
{0x3022, 0x24},
{0x3023, 0x24},
{0x3002, 0x00},
{0x3003, 0xA4},
{0x3004, 0x00},
{0x3005, 0x04},
{0x3006, 0x04},
{0x3007, 0x63},
{0x3008, 0x02},
{0x3009, 0xD3},
{0x300A, 0x05},
{0x300B, 0x3C},
{0x300C, 0x02},
{0x300D, 0xE0},
{0x300E, 0x03},
{0x300F, 0xC0},
{0x3010, 0x02},
{0x3011, 0xD0},
{0x32B8, 0x3F},
{0x32B9, 0x31},
{0x32BB, 0x87},
{0x32BC, 0x38},
{0x32BD, 0x3C},
{0x32BE, 0x34},
{0x3201, 0x7F},
{0x3021, 0x06},
{0x3025, 0x00}, //normal
{0x3400, 0x01},
{0x3060, 0x01},
{REGLIST_TAIL, 0x00}, // tail
};
static const DRAM_ATTR uint16_t sensor_framesize_QVGA[][2] = {
//[JPEG_320x240_10.14_10.14_Fps]
{0x3021, 0x00},
{REG_DLY, 100}, // delay 100ms
{0x32BF, 0x60},
{0x32C0, 0x5A},
{0x32C1, 0x5A},
{0x32C2, 0x5A},
{0x32C3, 0x00},
{0x32C4, 0x20},
{0x32C5, 0x20},
{0x32C6, 0x20},
{0x32C7, 0x00},
{0x32C8, 0x4B},
{0x32C9, 0x5A},
{0x32CA, 0x7A},
{0x32CB, 0x7A},
{0x32CC, 0x7A},
{0x32CD, 0x7A},
{0x32DB, 0x62},
{0x32F0, 0x70},
{0x3400, 0x08},
{0x3400, 0x00},
{0x3401, 0x4E},
{0x3404, 0x00},
{0x3405, 0x00},
{0x3410, 0x00},
{0x32E0, 0x01},
{0x32E1, 0x40},
{0x32E2, 0x00},
{0x32E3, 0xF0},
{0x32E4, 0x02},
{0x32E5, 0x02},
{0x32E6, 0x02},
{0x32E7, 0x03},
{0x3200, 0x3E},
{0x3201, 0x0F},
{0x3028, 0x0F},
{0x3029, 0x00},
{0x302A, 0x08},
{0x3022, 0x24},
{0x3023, 0x24},
{0x3002, 0x00},
{0x3003, 0xA4},
{0x3004, 0x00},
{0x3005, 0x04},
{0x3006, 0x04},
{0x3007, 0x63},
{0x3008, 0x02},
{0x3009, 0xD3},
{0x300A, 0x05},
{0x300B, 0x3C},
{0x300C, 0x02},
{0x300D, 0xE0},
{0x300E, 0x03},
{0x300F, 0xC0},
{0x3010, 0x02},
{0x3011, 0xD0},
{0x32B8, 0x3F},
{0x32B9, 0x31},
{0x32BB, 0x87},
{0x32BC, 0x38},
{0x32BD, 0x3C},
{0x32BE, 0x34},
{0x3201, 0x7F},
{0x3021, 0x06},
{0x3025, 0x00}, //normal
{0x3400, 0x01},
{0x3060, 0x01},
{REGLIST_TAIL, 0x00}, // tail
};
static const DRAM_ATTR uint16_t sensor_framesize_VGA_xyskip[][2] = {
// [JPEG_640x360_20.00_25.01_Fps_XY_Skip]
// Set_Device_Format = FORMAT_16_8
// SET_Device_Addr = 0x54
{0x3021, 0x00},
{REG_DLY, 100}, // delay 100ms
{0x32BF, 0x60 },
{0x320A, 0xB2 },
{0x32C0, 0x64 },
{0x32C1, 0x64 },
{0x32C2, 0x64 },
{0x32C3, 0x00 },
{0x32C4, 0x20 },
{0x32C5, 0x20 },
{0x32C6, 0x20 },
{0x32C7, 0x00 },
{0x32C8, 0x62 },
{0x32C9, 0x64 },
{0x32CA, 0x84 },
{0x32CB, 0x84 },
{0x32CC, 0x84 },
{0x32CD, 0x84 },
{0x32DB, 0x68 },
{0x32F0, 0x70 },
{0x3400, 0x08 },
{0x3400, 0x00 },
{0x3401, 0x4E },
{0x3404, 0x00 },
{0x3405, 0x00 },
{0x3410, 0x00 },
{0x3200, 0x3E },
{0x3201, 0x0F },
{0x3028, 0x0F },
{0x3029, 0x00 },
{0x302A, 0x08 },
{0x3022, 0x24 },
{0x3023, 0x6C },
{0x3002, 0x00 },
{0x3003, 0x04 },
{0x3004, 0x00 },
{0x3005, 0x04 },
{0x3006, 0x05 },
{0x3007, 0x03 },
{0x3008, 0x02 },
{0x3009, 0xD3 },
{0x300A, 0x03 },
{0x300B, 0xFC },
{0x300C, 0x01 },
{0x300D, 0x88 },
{0x300E, 0x02 },
{0x300F, 0x80 },
{0x3010, 0x01 },
{0x3011, 0x68 },
{0x32B8, 0x3F },
{0x32B9, 0x31 },
{0x32BB, 0x87 },
{0x32BC, 0x38 },
{0x32BD, 0x3C },
{0x32BE, 0x34 },
{0x3201, 0x3F },
{0x3025, 0x00 }, //normal
{0x3021, 0x06 },
{0x3400, 0x01 },
{0x3060, 0x01 },
{REGLIST_TAIL, 0x00}, // tail
};
static const DRAM_ATTR uint16_t sensor_framesize_VGA_xskip[][2] = {
//[JPEG_640x480_Xskip_13.32_13.32_Fps]
{0x3021, 0x00},
{REG_DLY, 100}, // delay 100ms
{0x32BF, 0x60},
{0x32C0, 0x5A},
{0x32C1, 0x5A},
{0x32C2, 0x5A},
{0x32C3, 0x00},
{0x32C4, 0x20},
{0x32C5, 0x20},
{0x32C6, 0x20},
{0x32C7, 0x00},
{0x32C8, 0x62},
{0x32C9, 0x5A},
{0x32CA, 0x7A},
{0x32CB, 0x7A},
{0x32CC, 0x7A},
{0x32CD, 0x7A},
{0x32DB, 0x68},
{0x32F0, 0x70},
{0x3400, 0x08},
{0x3400, 0x00},
{0x3401, 0x4E},
{0x3404, 0x00},
{0x3405, 0x00},
{0x3410, 0x00},
{0x32E0, 0x02},
{0x32E1, 0x80},
{0x32E2, 0x01},
{0x32E3, 0xE0},
{0x32E4, 0x00},
{0x32E5, 0x00},
{0x32E6, 0x00},
{0x32E7, 0x80},
{0x3200, 0x3E},
{0x3201, 0x0F},
{0x3028, 0x0F},
{0x3029, 0x00},
{0x302A, 0x08},
{0x3022, 0x24},
{0x3023, 0x2C},
{0x3002, 0x00},
{0x3003, 0x04},
{0x3004, 0x00},
{0x3005, 0x04},
{0x3006, 0x05},
{0x3007, 0x03},
{0x3008, 0x02},
{0x3009, 0xD3},
{0x300A, 0x03},
{0x300B, 0xFC},
{0x300C, 0x02},
{0x300D, 0xE0},
{0x300E, 0x02},
{0x300F, 0x80},
{0x3010, 0x02},
{0x3011, 0xD0},
{0x32B8, 0x3F},
{0x32B9, 0x31},
{0x32BB, 0x87},
{0x32BC, 0x38},
{0x32BD, 0x3C},
{0x32BE, 0x34},
{0x3201, 0x7F},
{0x3021, 0x06},
{0x3025, 0x00}, //normal
{0x3400, 0x01},
{0x3060, 0x01},
{REGLIST_TAIL, 0x00}, // tail
};
static const DRAM_ATTR uint16_t sensor_framesize_QVGA_xskip[][2] = {
{0x3021, 0x00},
{REG_DLY, 100}, // delay 100ms
//[JPEG_320x240_Xskip_13.32_13.32_Fps]
{0x32BF, 0x60},
{0x32C0, 0x5A},
{0x32C1, 0x5A},
{0x32C2, 0x5A},
{0x32C3, 0x00},
{0x32C4, 0x20},
{0x32C5, 0x20},
{0x32C6, 0x20},
{0x32C7, 0x00},
{0x32C8, 0x62},
{0x32C9, 0x5A},
{0x32CA, 0x7A},
{0x32CB, 0x7A},
{0x32CC, 0x7A},
{0x32CD, 0x7A},
{0x32DB, 0x68},
{0x32F0, 0x70},
{0x3400, 0x08},
{0x3400, 0x00},
{0x3401, 0x4E},
{0x3404, 0x00},
{0x3405, 0x00},
{0x3410, 0x00},
{0x32E0, 0x01},
{0x32E1, 0x40},
{0x32E2, 0x00},
{0x32E3, 0xF0},
{0x32E4, 0x01},
{0x32E5, 0x01},
{0x32E6, 0x02},
{0x32E7, 0x03},
{0x3200, 0x3E},
{0x3201, 0x0F},
{0x3028, 0x0F},
{0x3029, 0x00},
{0x302A, 0x08},
{0x3022, 0x24},
{0x3023, 0x2C},
{0x3002, 0x00},
{0x3003, 0x04},
{0x3004, 0x00},
{0x3005, 0x04},
{0x3006, 0x05},
{0x3007, 0x03},
{0x3008, 0x02},
{0x3009, 0xD3},
{0x300A, 0x03},
{0x300B, 0xFC},
{0x300C, 0x02},
{0x300D, 0xE0},
{0x300E, 0x02},
{0x300F, 0x80},
{0x3010, 0x02},
{0x3011, 0xD0},
{0x32B8, 0x3F},
{0x32B9, 0x31},
{0x32BB, 0x87},
{0x32BC, 0x38},
{0x32BD, 0x3C},
{0x32BE, 0x34},
{0x3201, 0x7F},
{0x3021, 0x06},
{0x3025, 0x00}, //normal
{0x3400, 0x01},
{0x3060, 0x01},
{REGLIST_TAIL, 0x00}, // tail
};
static const DRAM_ATTR uint16_t sensor_framesize_VGA_crop[][2] = {
//[JPEG_640x480_Crop_19.77_19.77_Fps]
{0x3021, 0x00},
{REG_DLY, 100}, // delay 100ms
{0x32BF, 0x60},
{0x32C0, 0x5A},
{0x32C1, 0x5A},
{0x32C2, 0x5A},
{0x32C3, 0x00},
{0x32C4, 0x20},
{0x32C5, 0x20},
{0x32C6, 0x20},
{0x32C7, 0x00},
{0x32C8, 0x62},
{0x32C9, 0x5A},
{0x32CA, 0x7A},
{0x32CB, 0x7A},
{0x32CC, 0x7A},
{0x32CD, 0x7A},
{0x32DB, 0x68},
{0x32F0, 0x70},
{0x3400, 0x08},
{0x3400, 0x00},
{0x3401, 0x4E},
{0x3404, 0x00},
{0x3405, 0x00},
{0x3410, 0x00},
{0x3200, 0x3E},
{0x3201, 0x0F},
{0x3028, 0x0F},
{0x3029, 0x00},
{0x302A, 0x08},
{0x3022, 0x24},
{0x3023, 0x24},
{0x3002, 0x01},
{0x3003, 0x44},
{0x3004, 0x00},
{0x3005, 0x7C},
{0x3006, 0x03},
{0x3007, 0xC3},
{0x3008, 0x02},
{0x3009, 0x5B},
{0x300A, 0x03},
{0x300B, 0xFC},
{0x300C, 0x01},
{0x300D, 0xF0},
{0x300E, 0x02},
{0x300F, 0x80},
{0x3010, 0x01},
{0x3011, 0xE0},
{0x32B8, 0x3F},
{0x32B9, 0x31},
{0x32BB, 0x87},
{0x32BC, 0x38},
{0x32BD, 0x3C},
{0x32BE, 0x34},
{0x3201, 0x3F},
{0x3021, 0x06},
{0x3025, 0x00}, //normal
{0x3400, 0x01},
{0x3060, 0x01},
{REGLIST_TAIL, 0x00}, // tail
};
static const DRAM_ATTR uint16_t sensor_framesize_QVGA_crop[][2] = {
//[JPEG_320x240_Crop_19.77_19.77_Fps]
{0x3021, 0x00},
{REG_DLY, 100}, // delay 100ms
{0x32BF, 0x60},
{0x32C0, 0x5A},
{0x32C1, 0x5A},
{0x32C2, 0x5A},
{0x32C3, 0x00},
{0x32C4, 0x20},
{0x32C5, 0x20},
{0x32C6, 0x20},
{0x32C7, 0x00},
{0x32C8, 0x62},
{0x32C9, 0x5A},
{0x32CA, 0x7A},
{0x32CB, 0x7A},
{0x32CC, 0x7A},
{0x32CD, 0x7A},
{0x32DB, 0x68},
{0x32F0, 0x70},
{0x3400, 0x08},
{0x3400, 0x00},
{0x3401, 0x4E},
{0x3404, 0x00},
{0x3405, 0x00},
{0x3410, 0x00},
{0x32E0, 0x01},
{0x32E1, 0x40},
{0x32E2, 0x00},
{0x32E3, 0xF0},
{0x32E4, 0x01},
{0x32E5, 0x01},
{0x32E6, 0x01},
{0x32E7, 0x02},
{0x3200, 0x3E},
{0x3201, 0x0F},
{0x3028, 0x0F},
{0x3029, 0x00},
{0x302A, 0x08},
{0x3022, 0x24},
{0x3023, 0x24},
{0x3002, 0x01},
{0x3003, 0x44},
{0x3004, 0x00},
{0x3005, 0x7C},
{0x3006, 0x03},
{0x3007, 0xC3},
{0x3008, 0x02},
{0x3009, 0x5B},
{0x300A, 0x03},
{0x300B, 0xFC},
{0x300C, 0x01},
{0x300D, 0xF0},
{0x300E, 0x02},
{0x300F, 0x80},
{0x3010, 0x01},
{0x3011, 0xE0},
{0x32B8, 0x3F},
{0x32B9, 0x31},
{0x32BB, 0x87},
{0x32BC, 0x38},
{0x32BD, 0x3C},
{0x32BE, 0x34},
{0x3201, 0x7F},
{0x3021, 0x06},
{0x3025, 0x00}, //normal
{0x3400, 0x01},
{0x3060, 0x01},
{REGLIST_TAIL, 0x00}, // tail
};
#endif

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/*
* This file is part of the OpenMV project.
* Copyright (c) 2013/2014 Ibrahim Abdelkader <i.abdalkader@gmail.com>
* This work is licensed under the MIT license, see the file LICENSE for details.
*
* OV2640 driver.
*
*/
#ifndef __OV2640_H__
#define __OV2640_H__
#include "sensor.h"
int ov2640_init(sensor_t *sensor);
#endif // __OV2640_H__

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/*
* This file is part of the OpenMV project.
* Copyright (c) 2013/2014 Ibrahim Abdelkader <i.abdalkader@gmail.com>
* This work is licensed under the MIT license, see the file LICENSE for details.
*
* OV2640 register definitions.
*/
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
/* DSP register bank FF=0x00*/
#define R_BYPASS 0x05
#define QS 0x44
#define CTRLI 0x50
#define HSIZE 0x51
#define VSIZE 0x52
#define XOFFL 0x53
#define YOFFL 0x54
#define VHYX 0x55
#define DPRP 0x56
#define TEST 0x57
#define ZMOW 0x5A
#define ZMOH 0x5B
#define ZMHH 0x5C
#define BPADDR 0x7C
#define BPDATA 0x7D
#define CTRL2 0x86
#define CTRL3 0x87
#define SIZEL 0x8C
#define HSIZE8 0xC0
#define VSIZE8 0xC1
#define CTRL0 0xC2
#define CTRL1 0xC3
#define R_DVP_SP 0xD3
#define IMAGE_MODE 0xDA
#define RESET 0xE0
#define MS_SP 0xF0
#define SS_ID 0xF7
#define SS_CTRL 0xF7
#define MC_BIST 0xF9
#define MC_AL 0xFA
#define MC_AH 0xFB
#define MC_D 0xFC
#define P_CMD 0xFD
#define P_STATUS 0xFE
#define BANK_SEL 0xFF
#define CTRLI_LP_DP 0x80
#define CTRLI_ROUND 0x40
#define CTRL0_AEC_EN 0x80
#define CTRL0_AEC_SEL 0x40
#define CTRL0_STAT_SEL 0x20
#define CTRL0_VFIRST 0x10
#define CTRL0_YUV422 0x08
#define CTRL0_YUV_EN 0x04
#define CTRL0_RGB_EN 0x02
#define CTRL0_RAW_EN 0x01
#define CTRL2_DCW_EN 0x20
#define CTRL2_SDE_EN 0x10
#define CTRL2_UV_ADJ_EN 0x08
#define CTRL2_UV_AVG_EN 0x04
#define CTRL2_CMX_EN 0x01
#define CTRL3_BPC_EN 0x80
#define CTRL3_WPC_EN 0x40
#define R_DVP_SP_AUTO_MODE 0x80
#define R_BYPASS_DSP_EN 0x00
#define R_BYPASS_DSP_BYPAS 0x01
#define IMAGE_MODE_Y8_DVP_EN 0x40
#define IMAGE_MODE_JPEG_EN 0x10
#define IMAGE_MODE_YUV422 0x00
#define IMAGE_MODE_RAW10 0x04
#define IMAGE_MODE_RGB565 0x08
#define IMAGE_MODE_HREF_VSYNC 0x02
#define IMAGE_MODE_LBYTE_FIRST 0x01
#define RESET_MICROC 0x40
#define RESET_SCCB 0x20
#define RESET_JPEG 0x10
#define RESET_DVP 0x04
#define RESET_IPU 0x02
#define RESET_CIF 0x01
#define MC_BIST_RESET 0x80
#define MC_BIST_BOOT_ROM_SEL 0x40
#define MC_BIST_12KB_SEL 0x20
#define MC_BIST_12KB_MASK 0x30
#define MC_BIST_512KB_SEL 0x08
#define MC_BIST_512KB_MASK 0x0C
#define MC_BIST_BUSY_BIT_R 0x02
#define MC_BIST_MC_RES_ONE_SH_W 0x02
#define MC_BIST_LAUNCH 0x01
typedef enum {
BANK_DSP, BANK_SENSOR, BANK_MAX
} ov2640_bank_t;
/* Sensor register bank FF=0x01*/
#define GAIN 0x00
#define COM1 0x03
#define REG04 0x04
#define REG08 0x08
#define COM2 0x09
#define REG_PID 0x0A
#define REG_VER 0x0B
#define COM3 0x0C
#define COM4 0x0D
#define AEC 0x10
#define CLKRC 0x11
#define COM7 0x12
#define COM8 0x13
#define COM9 0x14 /* AGC gain ceiling */
#define COM10 0x15
#define HSTART 0x17
#define HSTOP 0x18
#define VSTART 0x19
#define VSTOP 0x1A
#define MIDH 0x1C
#define MIDL 0x1D
#define AEW 0x24
#define AEB 0x25
#define VV 0x26
#define REG2A 0x2A
#define FRARL 0x2B
#define ADDVSL 0x2D
#define ADDVSH 0x2E
#define YAVG 0x2F
#define HSDY 0x30
#define HEDY 0x31
#define REG32 0x32
#define ARCOM2 0x34
#define REG45 0x45
#define FLL 0x46
#define FLH 0x47
#define COM19 0x48
#define ZOOMS 0x49
#define COM22 0x4B
#define COM25 0x4E
#define BD50 0x4F
#define BD60 0x50
#define REG5D 0x5D
#define REG5E 0x5E
#define REG5F 0x5F
#define REG60 0x60
#define HISTO_LOW 0x61
#define HISTO_HIGH 0x62
#define REG04_DEFAULT 0x28
#define REG04_HFLIP_IMG 0x80
#define REG04_VFLIP_IMG 0x40
#define REG04_VREF_EN 0x10
#define REG04_HREF_EN 0x08
#define REG04_SET(x) (REG04_DEFAULT|x)
#define COM2_STDBY 0x10
#define COM2_OUT_DRIVE_1x 0x00
#define COM2_OUT_DRIVE_2x 0x01
#define COM2_OUT_DRIVE_3x 0x02
#define COM2_OUT_DRIVE_4x 0x03
#define COM3_DEFAULT 0x38
#define COM3_BAND_50Hz 0x04
#define COM3_BAND_60Hz 0x00
#define COM3_BAND_AUTO 0x02
#define COM3_BAND_SET(x) (COM3_DEFAULT|x)
#define COM7_SRST 0x80
#define COM7_RES_UXGA 0x00 /* UXGA */
#define COM7_RES_SVGA 0x40 /* SVGA */
#define COM7_RES_CIF 0x20 /* CIF */
#define COM7_ZOOM_EN 0x04 /* Enable Zoom */
#define COM7_COLOR_BAR 0x02 /* Enable Color Bar Test */
#define COM8_DEFAULT 0xC0
#define COM8_BNDF_EN 0x20 /* Enable Banding filter */
#define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */
#define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */
#define COM8_SET(x) (COM8_DEFAULT|x)
#define COM9_DEFAULT 0x08
#define COM9_AGC_GAIN_2x 0x00 /* AGC: 2x */
#define COM9_AGC_GAIN_4x 0x01 /* AGC: 4x */
#define COM9_AGC_GAIN_8x 0x02 /* AGC: 8x */
#define COM9_AGC_GAIN_16x 0x03 /* AGC: 16x */
#define COM9_AGC_GAIN_32x 0x04 /* AGC: 32x */
#define COM9_AGC_GAIN_64x 0x05 /* AGC: 64x */
#define COM9_AGC_GAIN_128x 0x06 /* AGC: 128x */
#define COM9_AGC_SET(x) (COM9_DEFAULT|(x<<5))
#define COM10_HREF_EN 0x80 /* HSYNC changes to HREF */
#define COM10_HSYNC_EN 0x40 /* HREF changes to HSYNC */
#define COM10_PCLK_FREE 0x20 /* PCLK output option: free running PCLK */
#define COM10_PCLK_EDGE 0x10 /* Data is updated at the rising edge of PCLK */
#define COM10_HREF_NEG 0x08 /* HREF negative */
#define COM10_VSYNC_NEG 0x02 /* VSYNC negative */
#define COM10_HSYNC_NEG 0x01 /* HSYNC negative */
#define CTRL1_AWB 0x08 /* Enable AWB */
#define VV_AGC_TH_SET(h,l) ((h<<4)|(l&0x0F))
#define REG32_UXGA 0x36
#define REG32_SVGA 0x09
#define REG32_CIF 0x89
#define CLKRC_2X 0x80
#define CLKRC_2X_UXGA (0x01 | CLKRC_2X)
#define CLKRC_2X_SVGA CLKRC_2X
#define CLKRC_2X_CIF CLKRC_2X
#endif //__REG_REGS_H__

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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _OV2640_SETTINGS_H_
#define _OV2640_SETTINGS_H_
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "ov2640_regs.h"
typedef enum {
OV2640_MODE_UXGA, OV2640_MODE_SVGA, OV2640_MODE_CIF, OV2640_MODE_MAX
} ov2640_sensor_mode_t;
typedef struct {
union {
struct {
uint8_t pclk_div:7;
uint8_t pclk_auto:1;
};
uint8_t pclk;
};
union {
struct {
uint8_t clk_div:6;
uint8_t reserved:1;
uint8_t clk_2x:1;
};
uint8_t clk;
};
} ov2640_clk_t;
typedef struct {
uint16_t offset_x;
uint16_t offset_y;
uint16_t max_x;
uint16_t max_y;
} ov2640_ratio_settings_t;
static const DRAM_ATTR ov2640_ratio_settings_t ratio_table[] = {
// ox, oy, mx, my
{ 0, 0, 1600, 1200 }, //4x3
{ 8, 72, 1584, 1056 }, //3x2
{ 0, 100, 1600, 1000 }, //16x10
{ 0, 120, 1600, 960 }, //5x3
{ 0, 150, 1600, 900 }, //16x9
{ 2, 258, 1596, 684 }, //21x9
{ 50, 0, 1500, 1200 }, //5x4
{ 200, 0, 1200, 1200 }, //1x1
{ 462, 0, 676, 1200 } //9x16
};
// 30fps@24MHz
const DRAM_ATTR uint8_t ov2640_settings_cif[][2] = {
{BANK_SEL, BANK_DSP},
{0x2c, 0xff},
{0x2e, 0xdf},
{BANK_SEL, BANK_SENSOR},
{0x3c, 0x32},
{CLKRC, 0x01},
{COM2, COM2_OUT_DRIVE_3x},
{REG04, REG04_DEFAULT},
{COM8, COM8_DEFAULT | COM8_BNDF_EN | COM8_AGC_EN | COM8_AEC_EN},
{COM9, COM9_AGC_SET(COM9_AGC_GAIN_8x)},
{0x2c, 0x0c},
{0x33, 0x78},
{0x3a, 0x33},
{0x3b, 0xfB},
{0x3e, 0x00},
{0x43, 0x11},
{0x16, 0x10},
{0x39, 0x92},
{0x35, 0xda},
{0x22, 0x1a},
{0x37, 0xc3},
{0x23, 0x00},
{ARCOM2, 0xc0},
{0x06, 0x88},
{0x07, 0xc0},
{COM4, 0x87},
{0x0e, 0x41},
{0x4c, 0x00},
{0x4a, 0x81},
{0x21, 0x99},
{AEW, 0x40},
{AEB, 0x38},
{VV, VV_AGC_TH_SET(8,2)},
{0x5c, 0x00},
{0x63, 0x00},
{HISTO_LOW, 0x70},
{HISTO_HIGH, 0x80},
{0x7c, 0x05},
{0x20, 0x80},
{0x28, 0x30},
{0x6c, 0x00},
{0x6d, 0x80},
{0x6e, 0x00},
{0x70, 0x02},
{0x71, 0x94},
{0x73, 0xc1},
{0x3d, 0x34},
{0x5a, 0x57},
{BD50, 0xbb},
{BD60, 0x9c},
{COM7, COM7_RES_CIF},
{HSTART, 0x11},
{HSTOP, 0x43},
{VSTART, 0x00},
{VSTOP, 0x25},
{REG32, 0x89},
{0x37, 0xc0},
{BD50, 0xca},
{BD60, 0xa8},
{0x6d, 0x00},
{0x3d, 0x38},
{BANK_SEL, BANK_DSP},
{0xe5, 0x7f},
{MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL},
{0x41, 0x24},
{RESET, RESET_JPEG | RESET_DVP},
{0x76, 0xff},
{0x33, 0xa0},
{0x42, 0x20},
{0x43, 0x18},
{0x4c, 0x00},
{CTRL3, CTRL3_WPC_EN | 0x10 },
{0x88, 0x3f},
{0xd7, 0x03},
{0xd9, 0x10},
{R_DVP_SP, R_DVP_SP_AUTO_MODE | 0x02},
{0xc8, 0x08},
{0xc9, 0x80},
{BPADDR, 0x00},
{BPDATA, 0x00},
{BPADDR, 0x03},
{BPDATA, 0x48},
{BPDATA, 0x48},
{BPADDR, 0x08},
{BPDATA, 0x20},
{BPDATA, 0x10},
{BPDATA, 0x0e},
{0x90, 0x00},
{0x91, 0x0e},
{0x91, 0x1a},
{0x91, 0x31},
{0x91, 0x5a},
{0x91, 0x69},
{0x91, 0x75},
{0x91, 0x7e},
{0x91, 0x88},
{0x91, 0x8f},
{0x91, 0x96},
{0x91, 0xa3},
{0x91, 0xaf},
{0x91, 0xc4},
{0x91, 0xd7},
{0x91, 0xe8},
{0x91, 0x20},
{0x92, 0x00},
{0x93, 0x06},
{0x93, 0xe3},
{0x93, 0x05},
{0x93, 0x05},
{0x93, 0x00},
{0x93, 0x04},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x93, 0x00},
{0x96, 0x00},
{0x97, 0x08},
{0x97, 0x19},
{0x97, 0x02},
{0x97, 0x0c},
{0x97, 0x24},
{0x97, 0x30},
{0x97, 0x28},
{0x97, 0x26},
{0x97, 0x02},
{0x97, 0x98},
{0x97, 0x80},
{0x97, 0x00},
{0x97, 0x00},
{0xa4, 0x00},
{0xa8, 0x00},
{0xc5, 0x11},
{0xc6, 0x51},
{0xbf, 0x80},
{0xc7, 0x10},
{0xb6, 0x66},
{0xb8, 0xA5},
{0xb7, 0x64},
{0xb9, 0x7C},
{0xb3, 0xaf},
{0xb4, 0x97},
{0xb5, 0xFF},
{0xb0, 0xC5},
{0xb1, 0x94},
{0xb2, 0x0f},
{0xc4, 0x5c},
{CTRL1, 0xfd},
{0x7f, 0x00},
{0xe5, 0x1f},
{0xe1, 0x67},
{0xdd, 0x7f},
{IMAGE_MODE, 0x00},
{RESET, 0x00},
{R_BYPASS, R_BYPASS_DSP_EN},
{0, 0}
};
const DRAM_ATTR uint8_t ov2640_settings_to_cif[][2] = {
{BANK_SEL, BANK_SENSOR},
{COM7, COM7_RES_CIF},
//Set the sensor output window
{COM1, 0x0A},
{REG32, REG32_CIF},
{HSTART, 0x11},
{HSTOP, 0x43},
{VSTART, 0x00},
{VSTOP, 0x25},
//{CLKRC, 0x00},
{BD50, 0xca},
{BD60, 0xa8},
{0x5a, 0x23},
{0x6d, 0x00},
{0x3d, 0x38},
{0x39, 0x92},
{0x35, 0xda},
{0x22, 0x1a},
{0x37, 0xc3},
{0x23, 0x00},
{ARCOM2, 0xc0},
{0x06, 0x88},
{0x07, 0xc0},
{COM4, 0x87},
{0x0e, 0x41},
{0x4c, 0x00},
{BANK_SEL, BANK_DSP},
{RESET, RESET_DVP},
//Set the sensor resolution (UXGA, SVGA, CIF)
{HSIZE8, 0x32},
{VSIZE8, 0x25},
{SIZEL, 0x00},
//Set the image window size >= output size
{HSIZE, 0x64},
{VSIZE, 0x4a},
{XOFFL, 0x00},
{YOFFL, 0x00},
{VHYX, 0x00},
{TEST, 0x00},
{CTRL2, CTRL2_DCW_EN | 0x1D},
{CTRLI, CTRLI_LP_DP | 0x00},
//{R_DVP_SP, 0x08},
{0, 0}
};
const DRAM_ATTR uint8_t ov2640_settings_to_svga[][2] = {
{BANK_SEL, BANK_SENSOR},
{COM7, COM7_RES_SVGA},
//Set the sensor output window
{COM1, 0x0A},
{REG32, REG32_SVGA},
{HSTART, 0x11},
{HSTOP, 0x43},
{VSTART, 0x00},
{VSTOP, 0x4b},
//{CLKRC, 0x00},
{0x37, 0xc0},
{BD50, 0xca},
{BD60, 0xa8},
{0x5a, 0x23},
{0x6d, 0x00},
{0x3d, 0x38},
{0x39, 0x92},
{0x35, 0xda},
{0x22, 0x1a},
{0x37, 0xc3},
{0x23, 0x00},
{ARCOM2, 0xc0},
{0x06, 0x88},
{0x07, 0xc0},
{COM4, 0x87},
{0x0e, 0x41},
{0x42, 0x03},
{0x4c, 0x00},
{BANK_SEL, BANK_DSP},
{RESET, RESET_DVP},
//Set the sensor resolution (UXGA, SVGA, CIF)
{HSIZE8, 0x64},
{VSIZE8, 0x4B},
{SIZEL, 0x00},
//Set the image window size >= output size
{HSIZE, 0xC8},
{VSIZE, 0x96},
{XOFFL, 0x00},
{YOFFL, 0x00},
{VHYX, 0x00},
{TEST, 0x00},
{CTRL2, CTRL2_DCW_EN | 0x1D},
{CTRLI, CTRLI_LP_DP | 0x00},
//{R_DVP_SP, 0x08},
{0, 0}
};
const DRAM_ATTR uint8_t ov2640_settings_to_uxga[][2] = {
{BANK_SEL, BANK_SENSOR},
{COM7, COM7_RES_UXGA},
//Set the sensor output window
{COM1, 0x0F},
{REG32, REG32_UXGA},
{HSTART, 0x11},
{HSTOP, 0x75},
{VSTART, 0x01},
{VSTOP, 0x97},
//{CLKRC, 0x00},
{0x3d, 0x34},
{BD50, 0xbb},
{BD60, 0x9c},
{0x5a, 0x57},
{0x6d, 0x80},
{0x39, 0x82},
{0x23, 0x00},
{0x07, 0xc0},
{0x4c, 0x00},
{0x35, 0x88},
{0x22, 0x0a},
{0x37, 0x40},
{ARCOM2, 0xa0},
{0x06, 0x02},
{COM4, 0xb7},
{0x0e, 0x01},
{0x42, 0x83},
{BANK_SEL, BANK_DSP},
{RESET, RESET_DVP},
//Set the sensor resolution (UXGA, SVGA, CIF)
{HSIZE8, 0xc8},
{VSIZE8, 0x96},
{SIZEL, 0x00},
//Set the image window size >= output size
{HSIZE, 0x90},
{VSIZE, 0x2c},
{XOFFL, 0x00},
{YOFFL, 0x00},
{VHYX, 0x88},
{TEST, 0x00},
{CTRL2, CTRL2_DCW_EN | 0x1d},
{CTRLI, 0x00},
//{R_DVP_SP, 0x06},
{0, 0}
};
const DRAM_ATTR uint8_t ov2640_settings_jpeg3[][2] = {
{BANK_SEL, BANK_DSP},
{RESET, RESET_JPEG | RESET_DVP},
{IMAGE_MODE, IMAGE_MODE_JPEG_EN | IMAGE_MODE_HREF_VSYNC},
{0xD7, 0x03},
{0xE1, 0x77},
{0xE5, 0x1F},
{0xD9, 0x10},
{0xDF, 0x80},
{0x33, 0x80},
{0x3C, 0x10},
{0xEB, 0x30},
{0xDD, 0x7F},
{RESET, 0x00},
{0, 0}
};
static const uint8_t ov2640_settings_yuv422[][2] = {
{BANK_SEL, BANK_DSP},
{RESET, RESET_DVP},
{IMAGE_MODE, IMAGE_MODE_YUV422},
{0xD7, 0x01},
{0xE1, 0x67},
{RESET, 0x00},
{0, 0},
};
static const uint8_t ov2640_settings_rgb565[][2] = {
{BANK_SEL, BANK_DSP},
{RESET, RESET_DVP},
{IMAGE_MODE, IMAGE_MODE_RGB565},
{0xD7, 0x03},
{0xE1, 0x77},
{RESET, 0x00},
{0, 0},
};
#define NUM_BRIGHTNESS_LEVELS (5)
static const uint8_t brightness_regs[NUM_BRIGHTNESS_LEVELS + 1][5] = {
{BPADDR, BPDATA, BPADDR, BPDATA, BPDATA },
{0x00, 0x04, 0x09, 0x00, 0x00 }, /* -2 */
{0x00, 0x04, 0x09, 0x10, 0x00 }, /* -1 */
{0x00, 0x04, 0x09, 0x20, 0x00 }, /* 0 */
{0x00, 0x04, 0x09, 0x30, 0x00 }, /* +1 */
{0x00, 0x04, 0x09, 0x40, 0x00 }, /* +2 */
};
#define NUM_CONTRAST_LEVELS (5)
static const uint8_t contrast_regs[NUM_CONTRAST_LEVELS + 1][7] = {
{BPADDR, BPDATA, BPADDR, BPDATA, BPDATA, BPDATA, BPDATA },
{0x00, 0x04, 0x07, 0x20, 0x18, 0x34, 0x06 }, /* -2 */
{0x00, 0x04, 0x07, 0x20, 0x1c, 0x2a, 0x06 }, /* -1 */
{0x00, 0x04, 0x07, 0x20, 0x20, 0x20, 0x06 }, /* 0 */
{0x00, 0x04, 0x07, 0x20, 0x24, 0x16, 0x06 }, /* +1 */
{0x00, 0x04, 0x07, 0x20, 0x28, 0x0c, 0x06 }, /* +2 */
};
#define NUM_SATURATION_LEVELS (5)
static const uint8_t saturation_regs[NUM_SATURATION_LEVELS + 1][5] = {
{BPADDR, BPDATA, BPADDR, BPDATA, BPDATA },
{0x00, 0x02, 0x03, 0x28, 0x28 }, /* -2 */
{0x00, 0x02, 0x03, 0x38, 0x38 }, /* -1 */
{0x00, 0x02, 0x03, 0x48, 0x48 }, /* 0 */
{0x00, 0x02, 0x03, 0x58, 0x58 }, /* +1 */
{0x00, 0x02, 0x03, 0x68, 0x68 }, /* +2 */
};
#define NUM_SPECIAL_EFFECTS (7)
static const uint8_t special_effects_regs[NUM_SPECIAL_EFFECTS + 1][5] = {
{BPADDR, BPDATA, BPADDR, BPDATA, BPDATA },
{0x00, 0X00, 0x05, 0X80, 0X80 }, /* no effect */
{0x00, 0X40, 0x05, 0X80, 0X80 }, /* negative */
{0x00, 0X18, 0x05, 0X80, 0X80 }, /* black and white */
{0x00, 0X18, 0x05, 0X40, 0XC0 }, /* reddish */
{0x00, 0X18, 0x05, 0X40, 0X40 }, /* greenish */
{0x00, 0X18, 0x05, 0XA0, 0X40 }, /* blue */
{0x00, 0X18, 0x05, 0X40, 0XA6 }, /* retro */
};
#define NUM_WB_MODES (4)
static const uint8_t wb_modes_regs[NUM_WB_MODES + 1][3] = {
{0XCC, 0XCD, 0XCE },
{0x5E, 0X41, 0x54 }, /* sunny */
{0x65, 0X41, 0x4F }, /* cloudy */
{0x52, 0X41, 0x66 }, /* office */
{0x42, 0X3F, 0x71 }, /* home */
};
#define NUM_AE_LEVELS (5)
static const uint8_t ae_levels_regs[NUM_AE_LEVELS + 1][3] = {
{ AEW, AEB, VV },
{0x20, 0X18, 0x60 },
{0x34, 0X1C, 0x00 },
{0x3E, 0X38, 0x81 },
{0x48, 0X40, 0x81 },
{0x58, 0X50, 0x92 },
};
const uint8_t agc_gain_tbl[31] = {
0x00, 0x10, 0x18, 0x30, 0x34, 0x38, 0x3C, 0x70, 0x72, 0x74, 0x76, 0x78, 0x7A, 0x7C, 0x7E, 0xF0,
0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0xFF
};
#endif /* _OV2640_SETTINGS_H_ */

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/*
* This file is part of the OpenMV project.
* Copyright (c) 2013/2014 Ibrahim Abdelkader <i.abdalkader@gmail.com>
* This work is licensed under the MIT license, see the file LICENSE for details.
*
* OV3660 driver.
*
*/
#ifndef __OV3660_H__
#define __OV3660_H__
#include "sensor.h"
int ov3660_init(sensor_t *sensor);
#endif // __OV3660_H__

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/*
* OV3660 register definitions.
*/
#ifndef __OV3660_REG_REGS_H__
#define __OV3660_REG_REGS_H__
/* system control registers */
#define SYSTEM_CTROL0 0x3008 // Bit[7]: Software reset
// Bit[6]: Software power down
// Bit[5]: Reserved
// Bit[4]: SRB clock SYNC enable
// Bit[3]: Isolation suspend select
// Bit[2:0]: Not used
/* output format control registers */
#define FORMAT_CTRL 0x501F // Format select
// Bit[2:0]:
// 000: YUV422
// 001: RGB
// 010: Dither
// 011: RAW after DPC
// 101: RAW after CIP
/* format control registers */
#define FORMAT_CTRL00 0x4300
/* frame control registers */
#define FRAME_CTRL01 0x4201 // Control Passed Frame Number When both ON and OFF number set to 0x00,frame control is in bypass mode
// Bit[7:4]: Not used
// Bit[3:0]: Frame ON number
#define FRAME_CTRL02 0x4202 // Control Masked Frame Number When both ON and OFF number set to 0x00,frame control is in bypass mode
// Bit[7:4]: Not used
// BIT[3:0]: Frame OFF number
/* ISP top control registers */
#define PRE_ISP_TEST_SETTING_1 0x503D // Bit[7]: Test enable
// 0: Test disable
// 1: Color bar enable
// Bit[6]: Rolling
// Bit[5]: Transparent
// Bit[4]: Square black and white
// Bit[3:2]: Color bar style
// 00: Standard 8 color bar
// 01: Gradual change at vertical mode 1
// 10: Gradual change at horizontal
// 11: Gradual change at vertical mode 2
// Bit[1:0]: Test select
// 00: Color bar
// 01: Random data
// 10: Square data
// 11: Black image
//exposure = {0x3500[3:0], 0x3501[7:0], 0x3502[7:0]} / 16 × tROW
/* AEC/AGC control functions */
#define AEC_PK_MANUAL 0x3503 // AEC Manual Mode Control
// Bit[7:6]: Reserved
// Bit[5]: Gain delay option
// Valid when 0x3503[4]=1’b0
// 0: Delay one frame latch
// 1: One frame latch
// Bit[4:2]: Reserved
// Bit[1]: AGC manual
// 0: Auto enable
// 1: Manual enable
// Bit[0]: AEC manual
// 0: Auto enable
// 1: Manual enable
//gain = {0x350A[1:0], 0x350B[7:0]} / 16
/* mirror and flip registers */
#define TIMING_TC_REG20 0x3820 // Timing Control Register
// Bit[2:1]: Vertical flip enable
// 00: Normal
// 11: Vertical flip
// Bit[0]: Vertical binning enable
#define TIMING_TC_REG21 0x3821 // Timing Control Register
// Bit[5]: Compression Enable
// Bit[2:1]: Horizontal mirror enable
// 00: Normal
// 11: Horizontal mirror
// Bit[0]: Horizontal binning enable
#define CLOCK_POL_CONTROL 0x4740// Bit[5]: PCLK polarity 0: active low
// 1: active high
// Bit[3]: Gate PCLK under VSYNC
// Bit[2]: Gate PCLK under HREF
// Bit[1]: HREF polarity
// 0: active low
// 1: active high
// Bit[0] VSYNC polarity
// 0: active low
// 1: active high
#define DRIVE_CAPABILITY 0x302c // Bit[7:6]:
// 00: 1x
// 01: 2x
// 10: 3x
// 11: 4x
#define X_ADDR_ST_H 0x3800 //Bit[3:0]: X address start[11:8]
#define X_ADDR_ST_L 0x3801 //Bit[7:0]: X address start[7:0]
#define Y_ADDR_ST_H 0x3802 //Bit[2:0]: Y address start[10:8]
#define Y_ADDR_ST_L 0x3803 //Bit[7:0]: Y address start[7:0]
#define X_ADDR_END_H 0x3804 //Bit[3:0]: X address end[11:8]
#define X_ADDR_END_L 0x3805 //Bit[7:0]:
#define Y_ADDR_END_H 0x3806 //Bit[2:0]: Y address end[10:8]
#define Y_ADDR_END_L 0x3807 //Bit[7:0]:
// Size after scaling
#define X_OUTPUT_SIZE_H 0x3808 //Bit[3:0]: DVP output horizontal width[11:8]
#define X_OUTPUT_SIZE_L 0x3809 //Bit[7:0]:
#define Y_OUTPUT_SIZE_H 0x380a //Bit[2:0]: DVP output vertical height[10:8]
#define Y_OUTPUT_SIZE_L 0x380b //Bit[7:0]:
#define X_TOTAL_SIZE_H 0x380c //Bit[3:0]: Total horizontal size[11:8]
#define X_TOTAL_SIZE_L 0x380d //Bit[7:0]:
#define Y_TOTAL_SIZE_H 0x380e //Bit[7:0]: Total vertical size[15:8]
#define Y_TOTAL_SIZE_L 0x380f //Bit[7:0]:
#define X_OFFSET_H 0x3810 //Bit[3:0]: ISP horizontal offset[11:8]
#define X_OFFSET_L 0x3811 //Bit[7:0]:
#define Y_OFFSET_H 0x3812 //Bit[2:0]: ISP vertical offset[10:8]
#define Y_OFFSET_L 0x3813 //Bit[7:0]:
#define X_INCREMENT 0x3814 //Bit[7:4]: Horizontal odd subsample increment
//Bit[3:0]: Horizontal even subsample increment
#define Y_INCREMENT 0x3815 //Bit[7:4]: Vertical odd subsample increment
//Bit[3:0]: Vertical even subsample increment
// Size before scaling
//#define X_INPUT_SIZE (X_ADDR_END - X_ADDR_ST + 1 - (2 * X_OFFSET))
//#define Y_INPUT_SIZE (Y_ADDR_END - Y_ADDR_ST + 1 - (2 * Y_OFFSET))
#define ISP_CONTROL_01 0x5001 // Bit[5]: Scale enable
// 0: Disable
// 1: Enable
#define SCALE_CTRL_1 0x5601 // Bit[6:4]: HDIV RW
// DCW scale times
// 000: DCW 1 time
// 001: DCW 2 times
// 010: DCW 4 times
// 100: DCW 8 times
// 101: DCW 16 times
// Others: DCW 16 times
// Bit[2:0]: VDIV RW
// DCW scale times
// 000: DCW 1 time
// 001: DCW 2 times
// 010: DCW 4 times
// 100: DCW 8 times
// 101: DCW 16 times
// Others: DCW 16 times
#define SCALE_CTRL_2 0x5602 // X_SCALE High Bits
#define SCALE_CTRL_3 0x5603 // X_SCALE Low Bits
#define SCALE_CTRL_4 0x5604 // Y_SCALE High Bits
#define SCALE_CTRL_5 0x5605 // Y_SCALE Low Bits
#define SCALE_CTRL_6 0x5606 // Bit[3:0]: V Offset
#define PCLK_RATIO 0x3824 // Bit[4:0]: PCLK ratio manual
#define VFIFO_CTRL0C 0x460C // Bit[1]: PCLK manual enable
// 0: Auto
// 1: Manual by PCLK_RATIO
#define VFIFO_X_SIZE_H 0x4602
#define VFIFO_X_SIZE_L 0x4603
#define VFIFO_Y_SIZE_H 0x4604
#define VFIFO_Y_SIZE_L 0x4605
#define SC_PLLS_CTRL0 0x303a // Bit[7]: PLLS bypass
#define SC_PLLS_CTRL1 0x303b // Bit[4:0]: PLLS multiplier
#define SC_PLLS_CTRL2 0x303c // Bit[6:4]: PLLS charge pump control
// Bit[3:0]: PLLS system divider
#define SC_PLLS_CTRL3 0x303d // Bit[5:4]: PLLS pre-divider
// 00: 1
// 01: 1.5
// 10: 2
// 11: 3
// Bit[2]: PLLS root-divider - 1
// Bit[1:0]: PLLS seld5
// 00: 1
// 01: 1
// 10: 2
// 11: 2.5
#define COMPRESSION_CTRL00 0x4400 //
#define COMPRESSION_CTRL01 0x4401 //
#define COMPRESSION_CTRL02 0x4402 //
#define COMPRESSION_CTRL03 0x4403 //
#define COMPRESSION_CTRL04 0x4404 //
#define COMPRESSION_CTRL05 0x4405 //
#define COMPRESSION_CTRL06 0x4406 //
#define COMPRESSION_CTRL07 0x4407 // Bit[5:0]: QS
#define COMPRESSION_ISI_CTRL 0x4408 //
#define COMPRESSION_CTRL09 0x4409 //
#define COMPRESSION_CTRL0a 0x440a //
#define COMPRESSION_CTRL0b 0x440b //
#define COMPRESSION_CTRL0c 0x440c //
#define COMPRESSION_CTRL0d 0x440d //
#define COMPRESSION_CTRL0E 0x440e //
/**
* @brief register value
*/
#define TEST_COLOR_BAR 0xC0 /* Enable Color Bar roling Test */
#define AEC_PK_MANUAL_AGC_MANUALEN 0x02 /* Enable AGC Manual enable */
#define AEC_PK_MANUAL_AEC_MANUALEN 0x01 /* Enable AEC Manual enable */
#define TIMING_TC_REG20_VFLIP 0x06 /* Vertical flip enable */
#define TIMING_TC_REG21_HMIRROR 0x06 /* Horizontal mirror enable */
#endif // __OV3660_REG_REGS_H__

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#ifndef _OV3660_SETTINGS_H_
#define _OV3660_SETTINGS_H_
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "ov3660_regs.h"
static const ratio_settings_t ratio_table[] = {
// mw, mh, sx, sy, ex, ey, ox, oy, tx, ty
{ 2048, 1536, 0, 0, 2079, 1547, 16, 6, 2300, 1564 }, //4x3
{ 1920, 1280, 64, 128, 2015, 1419, 16, 6, 2172, 1436 }, //3x2
{ 2048, 1280, 0, 128, 2079, 1419, 16, 6, 2300, 1436 }, //16x10
{ 1920, 1152, 64, 192, 2015, 1355, 16, 6, 2172, 1372 }, //5x3
{ 1920, 1080, 64, 242, 2015, 1333, 16, 6, 2172, 1322 }, //16x9
{ 2048, 880, 0, 328, 2079, 1219, 16, 6, 2300, 1236 }, //21x9
{ 1920, 1536, 64, 0, 2015, 1547, 16, 6, 2172, 1564 }, //5x4
{ 1536, 1536, 256, 0, 1823, 1547, 16, 6, 2044, 1564 }, //1x1
{ 864, 1536, 592, 0, 1487, 1547, 16, 6, 2044, 1564 } //9x16
};
#define REG_DLY 0xffff
#define REGLIST_TAIL 0x0000
static const DRAM_ATTR uint16_t sensor_default_regs[][2] = {
{SYSTEM_CTROL0, 0x82}, // software reset
{REG_DLY, 10}, // delay 10ms
{0x3103, 0x13},
{SYSTEM_CTROL0, 0x42},
{0x3017, 0xff},
{0x3018, 0xff},
{DRIVE_CAPABILITY, 0xc3},
{CLOCK_POL_CONTROL, 0x21},
{0x3611, 0x01},
{0x3612, 0x2d},
{0x3032, 0x00},
{0x3614, 0x80},
{0x3618, 0x00},
{0x3619, 0x75},
{0x3622, 0x80},
{0x3623, 0x00},
{0x3624, 0x03},
{0x3630, 0x52},
{0x3632, 0x07},
{0x3633, 0xd2},
{0x3704, 0x80},
{0x3708, 0x66},
{0x3709, 0x12},
{0x370b, 0x12},
{0x3717, 0x00},
{0x371b, 0x60},
{0x371c, 0x00},
{0x3901, 0x13},
{0x3600, 0x08},
{0x3620, 0x43},
{0x3702, 0x20},
{0x3739, 0x48},
{0x3730, 0x20},
{0x370c, 0x0c},
{0x3a18, 0x00},
{0x3a19, 0xf8},
{0x3000, 0x10},
{0x3004, 0xef},
{0x6700, 0x05},
{0x6701, 0x19},
{0x6702, 0xfd},
{0x6703, 0xd1},
{0x6704, 0xff},
{0x6705, 0xff},
{0x3c01, 0x80},
{0x3c00, 0x04},
{0x3a08, 0x00}, {0x3a09, 0x62}, //50Hz Band Width Step (10bit)
{0x3a0e, 0x08}, //50Hz Max Bands in One Frame (6 bit)
{0x3a0a, 0x00}, {0x3a0b, 0x52}, //60Hz Band Width Step (10bit)
{0x3a0d, 0x09}, //60Hz Max Bands in One Frame (6 bit)
{0x3a00, 0x3a},//night mode off
{0x3a14, 0x09},
{0x3a15, 0x30},
{0x3a02, 0x09},
{0x3a03, 0x30},
{COMPRESSION_CTRL0E, 0x08},
{0x4520, 0x0b},
{0x460b, 0x37},
{0x4713, 0x02},
{0x471c, 0xd0},
{0x5086, 0x00},
{0x5002, 0x00},
{0x501f, 0x00},
{SYSTEM_CTROL0, 0x02},
{0x5180, 0xff},
{0x5181, 0xf2},
{0x5182, 0x00},
{0x5183, 0x14},
{0x5184, 0x25},
{0x5185, 0x24},
{0x5186, 0x16},
{0x5187, 0x16},
{0x5188, 0x16},
{0x5189, 0x68},
{0x518a, 0x60},
{0x518b, 0xe0},
{0x518c, 0xb2},
{0x518d, 0x42},
{0x518e, 0x35},
{0x518f, 0x56},
{0x5190, 0x56},
{0x5191, 0xf8},
{0x5192, 0x04},
{0x5193, 0x70},
{0x5194, 0xf0},
{0x5195, 0xf0},
{0x5196, 0x03},
{0x5197, 0x01},
{0x5198, 0x04},
{0x5199, 0x12},
{0x519a, 0x04},
{0x519b, 0x00},
{0x519c, 0x06},
{0x519d, 0x82},
{0x519e, 0x38},
{0x5381, 0x1d},
{0x5382, 0x60},
{0x5383, 0x03},
{0x5384, 0x0c},
{0x5385, 0x78},
{0x5386, 0x84},
{0x5387, 0x7d},
{0x5388, 0x6b},
{0x5389, 0x12},
{0x538a, 0x01},
{0x538b, 0x98},
{0x5480, 0x01},
// {0x5481, 0x05},
// {0x5482, 0x09},
// {0x5483, 0x10},
// {0x5484, 0x3a},
// {0x5485, 0x4c},
// {0x5486, 0x5a},
// {0x5487, 0x68},
// {0x5488, 0x74},
// {0x5489, 0x80},
// {0x548a, 0x8e},
// {0x548b, 0xa4},
// {0x548c, 0xb4},
// {0x548d, 0xc8},
// {0x548e, 0xde},
// {0x548f, 0xf0},
// {0x5490, 0x15},
{0x5000, 0xa7},
{0x5800, 0x0C},
{0x5801, 0x09},
{0x5802, 0x0C},
{0x5803, 0x0C},
{0x5804, 0x0D},
{0x5805, 0x17},
{0x5806, 0x06},
{0x5807, 0x05},
{0x5808, 0x04},
{0x5809, 0x06},
{0x580a, 0x09},
{0x580b, 0x0E},
{0x580c, 0x05},
{0x580d, 0x01},
{0x580e, 0x01},
{0x580f, 0x01},
{0x5810, 0x05},
{0x5811, 0x0D},
{0x5812, 0x05},
{0x5813, 0x01},
{0x5814, 0x01},
{0x5815, 0x01},
{0x5816, 0x05},
{0x5817, 0x0D},
{0x5818, 0x08},
{0x5819, 0x06},
{0x581a, 0x05},
{0x581b, 0x07},
{0x581c, 0x0B},
{0x581d, 0x0D},
{0x581e, 0x12},
{0x581f, 0x0D},
{0x5820, 0x0E},
{0x5821, 0x10},
{0x5822, 0x10},
{0x5823, 0x1E},
{0x5824, 0x53},
{0x5825, 0x15},
{0x5826, 0x05},
{0x5827, 0x14},
{0x5828, 0x54},
{0x5829, 0x25},
{0x582a, 0x33},
{0x582b, 0x33},
{0x582c, 0x34},
{0x582d, 0x16},
{0x582e, 0x24},
{0x582f, 0x41},
{0x5830, 0x50},
{0x5831, 0x42},
{0x5832, 0x15},
{0x5833, 0x25},
{0x5834, 0x34},
{0x5835, 0x33},
{0x5836, 0x24},
{0x5837, 0x26},
{0x5838, 0x54},
{0x5839, 0x25},
{0x583a, 0x15},
{0x583b, 0x25},
{0x583c, 0x53},
{0x583d, 0xCF},
{0x3a0f, 0x30},
{0x3a10, 0x28},
{0x3a1b, 0x30},
{0x3a1e, 0x28},
{0x3a11, 0x60},
{0x3a1f, 0x14},
{0x5302, 0x28},
{0x5303, 0x20},
{0x5306, 0x1c}, //de-noise offset 1
{0x5307, 0x28}, //de-noise offset 2
{0x4002, 0xc5},
{0x4003, 0x81},
{0x4005, 0x12},
{0x5688, 0x11},
{0x5689, 0x11},
{0x568a, 0x11},
{0x568b, 0x11},
{0x568c, 0x11},
{0x568d, 0x11},
{0x568e, 0x11},
{0x568f, 0x11},
{0x5580, 0x06},
{0x5588, 0x00},
{0x5583, 0x40},
{0x5584, 0x2c},
{ISP_CONTROL_01, 0x83}, // turn color matrix, awb and SDE
{REGLIST_TAIL, 0x00}, // tail
};
static const DRAM_ATTR uint16_t sensor_fmt_jpeg[][2] = {
{FORMAT_CTRL, 0x00}, // YUV422
{FORMAT_CTRL00, 0x30}, // YUYV
{0x3002, 0x00},//0x1c to 0x00 !!!
{0x3006, 0xff},//0xc3 to 0xff !!!
{0x471c, 0x50},//0xd0 to 0x50 !!!
{REGLIST_TAIL, 0x00}, // tail
};
static const DRAM_ATTR uint16_t sensor_fmt_raw[][2] = {
{FORMAT_CTRL00, 0x00}, // RAW
{REGLIST_TAIL, 0x00}
};
static const DRAM_ATTR uint16_t sensor_fmt_grayscale[][2] = {
{FORMAT_CTRL, 0x00}, // YUV422
{FORMAT_CTRL00, 0x10}, // Y8
{REGLIST_TAIL, 0x00}
};
static const DRAM_ATTR uint16_t sensor_fmt_yuv422[][2] = {
{FORMAT_CTRL, 0x00}, // YUV422
{FORMAT_CTRL00, 0x30}, // YUYV
{REGLIST_TAIL, 0x00}
};
static const DRAM_ATTR uint16_t sensor_fmt_rgb565[][2] = {
{FORMAT_CTRL, 0x01}, // RGB
{FORMAT_CTRL00, 0x61}, // RGB565 (BGR)
{REGLIST_TAIL, 0x00}
};
static const DRAM_ATTR uint8_t sensor_saturation_levels[9][11] = {
{0x1d, 0x60, 0x03, 0x07, 0x48, 0x4f, 0x4b, 0x40, 0x0b, 0x01, 0x98},//-4
{0x1d, 0x60, 0x03, 0x08, 0x54, 0x5c, 0x58, 0x4b, 0x0d, 0x01, 0x98},//-3
{0x1d, 0x60, 0x03, 0x0a, 0x60, 0x6a, 0x64, 0x56, 0x0e, 0x01, 0x98},//-2
{0x1d, 0x60, 0x03, 0x0b, 0x6c, 0x77, 0x70, 0x60, 0x10, 0x01, 0x98},//-1
{0x1d, 0x60, 0x03, 0x0c, 0x78, 0x84, 0x7d, 0x6b, 0x12, 0x01, 0x98},//0
{0x1d, 0x60, 0x03, 0x0d, 0x84, 0x91, 0x8a, 0x76, 0x14, 0x01, 0x98},//+1
{0x1d, 0x60, 0x03, 0x0e, 0x90, 0x9e, 0x96, 0x80, 0x16, 0x01, 0x98},//+2
{0x1d, 0x60, 0x03, 0x10, 0x9c, 0xac, 0xa2, 0x8b, 0x17, 0x01, 0x98},//+3
{0x1d, 0x60, 0x03, 0x11, 0xa8, 0xb9, 0xaf, 0x96, 0x19, 0x01, 0x98},//+4
};
static const DRAM_ATTR uint8_t sensor_special_effects[7][4] = {
{0x06, 0x40, 0x2c, 0x08},//Normal
{0x46, 0x40, 0x28, 0x08},//Negative
{0x1e, 0x80, 0x80, 0x08},//Grayscale
{0x1e, 0x80, 0xc0, 0x08},//Red Tint
{0x1e, 0x60, 0x60, 0x08},//Green Tint
{0x1e, 0xa0, 0x40, 0x08},//Blue Tint
{0x1e, 0x40, 0xa0, 0x08},//Sepia
};
#endif

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#ifndef __OV5640_H__
#define __OV5640_H__
#include "sensor.h"
int ov5640_init(sensor_t *sensor);
#endif // __OV5640_H__

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/*
* OV5640 register definitions.
*/
#ifndef __OV5640_REG_REGS_H__
#define __OV5640_REG_REGS_H__
/* system control registers */
#define SYSTEM_CTROL0 0x3008 // Bit[7]: Software reset
// Bit[6]: Software power down
// Bit[5]: Reserved
// Bit[4]: SRB clock SYNC enable
// Bit[3]: Isolation suspend select
// Bit[2:0]: Not used
#define DRIVE_CAPABILITY 0x302c // Bit[7:6]:
// 00: 1x
// 01: 2x
// 10: 3x
// 11: 4x
#define SC_PLLS_CTRL0 0x303a // Bit[7]: PLLS bypass
#define SC_PLLS_CTRL1 0x303b // Bit[4:0]: PLLS multiplier
#define SC_PLLS_CTRL2 0x303c // Bit[6:4]: PLLS charge pump control
// Bit[3:0]: PLLS system divider
#define SC_PLLS_CTRL3 0x303d // Bit[5:4]: PLLS pre-divider
// 00: 1
// 01: 1.5
// 10: 2
// 11: 3
// Bit[2]: PLLS root-divider - 1
// Bit[1:0]: PLLS seld5
// 00: 1
// 01: 1
// 10: 2
// 11: 2.5
/* AEC/AGC control functions */
#define AEC_PK_MANUAL 0x3503 // AEC Manual Mode Control
// Bit[7:6]: Reserved
// Bit[5]: Gain delay option
// Valid when 0x3503[4]=1’b0
// 0: Delay one frame latch
// 1: One frame latch
// Bit[4:2]: Reserved
// Bit[1]: AGC manual
// 0: Auto enable
// 1: Manual enable
// Bit[0]: AEC manual
// 0: Auto enable
// 1: Manual enable
//gain = {0x350A[1:0], 0x350B[7:0]} / 16
#define X_ADDR_ST_H 0x3800 //Bit[3:0]: X address start[11:8]
#define X_ADDR_ST_L 0x3801 //Bit[7:0]: X address start[7:0]
#define Y_ADDR_ST_H 0x3802 //Bit[2:0]: Y address start[10:8]
#define Y_ADDR_ST_L 0x3803 //Bit[7:0]: Y address start[7:0]
#define X_ADDR_END_H 0x3804 //Bit[3:0]: X address end[11:8]
#define X_ADDR_END_L 0x3805 //Bit[7:0]:
#define Y_ADDR_END_H 0x3806 //Bit[2:0]: Y address end[10:8]
#define Y_ADDR_END_L 0x3807 //Bit[7:0]:
// Size after scaling
#define X_OUTPUT_SIZE_H 0x3808 //Bit[3:0]: DVP output horizontal width[11:8]
#define X_OUTPUT_SIZE_L 0x3809 //Bit[7:0]:
#define Y_OUTPUT_SIZE_H 0x380a //Bit[2:0]: DVP output vertical height[10:8]
#define Y_OUTPUT_SIZE_L 0x380b //Bit[7:0]:
#define X_TOTAL_SIZE_H 0x380c //Bit[3:0]: Total horizontal size[11:8]
#define X_TOTAL_SIZE_L 0x380d //Bit[7:0]:
#define Y_TOTAL_SIZE_H 0x380e //Bit[7:0]: Total vertical size[15:8]
#define Y_TOTAL_SIZE_L 0x380f //Bit[7:0]:
#define X_OFFSET_H 0x3810 //Bit[3:0]: ISP horizontal offset[11:8]
#define X_OFFSET_L 0x3811 //Bit[7:0]:
#define Y_OFFSET_H 0x3812 //Bit[2:0]: ISP vertical offset[10:8]
#define Y_OFFSET_L 0x3813 //Bit[7:0]:
#define X_INCREMENT 0x3814 //Bit[7:4]: Horizontal odd subsample increment
//Bit[3:0]: Horizontal even subsample increment
#define Y_INCREMENT 0x3815 //Bit[7:4]: Vertical odd subsample increment
//Bit[3:0]: Vertical even subsample increment
// Size before scaling
//#define X_INPUT_SIZE (X_ADDR_END - X_ADDR_ST + 1 - (2 * X_OFFSET))
//#define Y_INPUT_SIZE (Y_ADDR_END - Y_ADDR_ST + 1 - (2 * Y_OFFSET))
/* mirror and flip registers */
#define TIMING_TC_REG20 0x3820 // Timing Control Register
// Bit[2:1]: Vertical flip enable
// 00: Normal
// 11: Vertical flip
// Bit[0]: Vertical binning enable
#define TIMING_TC_REG21 0x3821 // Timing Control Register
// Bit[5]: Compression Enable
// Bit[2:1]: Horizontal mirror enable
// 00: Normal
// 11: Horizontal mirror
// Bit[0]: Horizontal binning enable
#define PCLK_RATIO 0x3824 // Bit[4:0]: PCLK ratio manual
/* frame control registers */
#define FRAME_CTRL01 0x4201 // Control Passed Frame Number When both ON and OFF number set to 0x00,frame control is in bypass mode
// Bit[7:4]: Not used
// Bit[3:0]: Frame ON number
#define FRAME_CTRL02 0x4202 // Control Masked Frame Number When both ON and OFF number set to 0x00,frame control is in bypass mode
// Bit[7:4]: Not used
// BIT[3:0]: Frame OFF number
/* format control registers */
#define FORMAT_CTRL00 0x4300
#define CLOCK_POL_CONTROL 0x4740// Bit[5]: PCLK polarity 0: active low
// 1: active high
// Bit[3]: Gate PCLK under VSYNC
// Bit[2]: Gate PCLK under HREF
// Bit[1]: HREF polarity
// 0: active low
// 1: active high
// Bit[0] VSYNC polarity
// 0: active low
// 1: active high
#define ISP_CONTROL_01 0x5001 // Bit[5]: Scale enable
// 0: Disable
// 1: Enable
/* output format control registers */
#define FORMAT_CTRL 0x501F // Format select
// Bit[2:0]:
// 000: YUV422
// 001: RGB
// 010: Dither
// 011: RAW after DPC
// 101: RAW after CIP
/* ISP top control registers */
#define PRE_ISP_TEST_SETTING_1 0x503D // Bit[7]: Test enable
// 0: Test disable
// 1: Color bar enable
// Bit[6]: Rolling
// Bit[5]: Transparent
// Bit[4]: Square black and white
// Bit[3:2]: Color bar style
// 00: Standard 8 color bar
// 01: Gradual change at vertical mode 1
// 10: Gradual change at horizontal
// 11: Gradual change at vertical mode 2
// Bit[1:0]: Test select
// 00: Color bar
// 01: Random data
// 10: Square data
// 11: Black image
//exposure = {0x3500[3:0], 0x3501[7:0], 0x3502[7:0]} / 16 × tROW
#define SCALE_CTRL_1 0x5601 // Bit[6:4]: HDIV RW
// DCW scale times
// 000: DCW 1 time
// 001: DCW 2 times
// 010: DCW 4 times
// 100: DCW 8 times
// 101: DCW 16 times
// Others: DCW 16 times
// Bit[2:0]: VDIV RW
// DCW scale times
// 000: DCW 1 time
// 001: DCW 2 times
// 010: DCW 4 times
// 100: DCW 8 times
// 101: DCW 16 times
// Others: DCW 16 times
#define SCALE_CTRL_2 0x5602 // X_SCALE High Bits
#define SCALE_CTRL_3 0x5603 // X_SCALE Low Bits
#define SCALE_CTRL_4 0x5604 // Y_SCALE High Bits
#define SCALE_CTRL_5 0x5605 // Y_SCALE Low Bits
#define SCALE_CTRL_6 0x5606 // Bit[3:0]: V Offset
#define VFIFO_CTRL0C 0x460C // Bit[1]: PCLK manual enable
// 0: Auto
// 1: Manual by PCLK_RATIO
#define VFIFO_X_SIZE_H 0x4602
#define VFIFO_X_SIZE_L 0x4603
#define VFIFO_Y_SIZE_H 0x4604
#define VFIFO_Y_SIZE_L 0x4605
#define COMPRESSION_CTRL00 0x4400 //
#define COMPRESSION_CTRL01 0x4401 //
#define COMPRESSION_CTRL02 0x4402 //
#define COMPRESSION_CTRL03 0x4403 //
#define COMPRESSION_CTRL04 0x4404 //
#define COMPRESSION_CTRL05 0x4405 //
#define COMPRESSION_CTRL06 0x4406 //
#define COMPRESSION_CTRL07 0x4407 // Bit[5:0]: QS
#define COMPRESSION_ISI_CTRL 0x4408 //
#define COMPRESSION_CTRL09 0x4409 //
#define COMPRESSION_CTRL0a 0x440a //
#define COMPRESSION_CTRL0b 0x440b //
#define COMPRESSION_CTRL0c 0x440c //
#define COMPRESSION_CTRL0d 0x440d //
#define COMPRESSION_CTRL0E 0x440e //
/**
* @brief register value
*/
#define TEST_COLOR_BAR 0xC0 /* Enable Color Bar roling Test */
#define AEC_PK_MANUAL_AGC_MANUALEN 0x02 /* Enable AGC Manual enable */
#define AEC_PK_MANUAL_AEC_MANUALEN 0x01 /* Enable AEC Manual enable */
#define TIMING_TC_REG20_VFLIP 0x06 /* Vertical flip enable */
#define TIMING_TC_REG21_HMIRROR 0x06 /* Horizontal mirror enable */
#endif // __OV3660_REG_REGS_H__

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#ifndef _OV5640_SETTINGS_H_
#define _OV5640_SETTINGS_H_
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "ov5640_regs.h"
static const ratio_settings_t ratio_table[] = {
// mw, mh, sx, sy, ex, ey, ox, oy, tx, ty
{ 2560, 1920, 0, 0, 2623, 1951, 32, 16, 2844, 1968 }, //4x3
{ 2560, 1704, 0, 110, 2623, 1843, 32, 16, 2844, 1752 }, //3x2
{ 2560, 1600, 0, 160, 2623, 1791, 32, 16, 2844, 1648 }, //16x10
{ 2560, 1536, 0, 192, 2623, 1759, 32, 16, 2844, 1584 }, //5x3
{ 2560, 1440, 0, 240, 2623, 1711, 32, 16, 2844, 1488 }, //16x9
{ 2560, 1080, 0, 420, 2623, 1531, 32, 16, 2844, 1128 }, //21x9
{ 2400, 1920, 80, 0, 2543, 1951, 32, 16, 2684, 1968 }, //5x4
{ 1920, 1920, 320, 0, 2543, 1951, 32, 16, 2684, 1968 }, //1x1
{ 1088, 1920, 736, 0, 1887, 1951, 32, 16, 1884, 1968 } //9x16
};
#define REG_DLY 0xffff
#define REGLIST_TAIL 0x0000
static const DRAM_ATTR uint16_t sensor_default_regs[][2] = {
{SYSTEM_CTROL0, 0x82}, // software reset
{REG_DLY, 10}, // delay 10ms
{SYSTEM_CTROL0, 0x42}, // power down
//enable pll
{0x3103, 0x13},
//io direction
{0x3017, 0xff},
{0x3018, 0xff},
{DRIVE_CAPABILITY, 0xc3},
{CLOCK_POL_CONTROL, 0x21},
{0x4713, 0x02},//jpg mode select
{ISP_CONTROL_01, 0x83}, // turn color matrix, awb and SDE
//sys reset
{0x3000, 0x00},
{0x3002, 0x1c},
//clock enable
{0x3004, 0xff},
{0x3006, 0xc3},
//isp control
{0x5000, 0xa7},
{ISP_CONTROL_01, 0xa3},//+scaling?
{0x5003, 0x08},//special_effect
//unknown
{0x370c, 0x02},//!!IMPORTANT
{0x3634, 0x40},//!!IMPORTANT
//AEC/AGC
{0x3a02, 0x03},
{0x3a03, 0xd8},
{0x3a08, 0x01},
{0x3a09, 0x27},
{0x3a0a, 0x00},
{0x3a0b, 0xf6},
{0x3a0d, 0x04},
{0x3a0e, 0x03},
{0x3a0f, 0x30},//ae_level
{0x3a10, 0x28},//ae_level
{0x3a11, 0x60},//ae_level
{0x3a13, 0x43},
{0x3a14, 0x03},
{0x3a15, 0xd8},
{0x3a18, 0x00},//gainceiling
{0x3a19, 0xf8},//gainceiling
{0x3a1b, 0x30},//ae_level
{0x3a1e, 0x26},//ae_level
{0x3a1f, 0x14},//ae_level
//vcm debug
{0x3600, 0x08},
{0x3601, 0x33},
//50/60Hz
{0x3c01, 0xa4},
{0x3c04, 0x28},
{0x3c05, 0x98},
{0x3c06, 0x00},
{0x3c07, 0x08},
{0x3c08, 0x00},
{0x3c09, 0x1c},
{0x3c0a, 0x9c},
{0x3c0b, 0x40},
{0x460c, 0x22},//disable jpeg footer
//BLC
{0x4001, 0x02},
{0x4004, 0x02},
//AWB
{0x5180, 0xff},
{0x5181, 0xf2},
{0x5182, 0x00},
{0x5183, 0x14},
{0x5184, 0x25},
{0x5185, 0x24},
{0x5186, 0x09},
{0x5187, 0x09},
{0x5188, 0x09},
{0x5189, 0x75},
{0x518a, 0x54},
{0x518b, 0xe0},
{0x518c, 0xb2},
{0x518d, 0x42},
{0x518e, 0x3d},
{0x518f, 0x56},
{0x5190, 0x46},
{0x5191, 0xf8},
{0x5192, 0x04},
{0x5193, 0x70},
{0x5194, 0xf0},
{0x5195, 0xf0},
{0x5196, 0x03},
{0x5197, 0x01},
{0x5198, 0x04},
{0x5199, 0x12},
{0x519a, 0x04},
{0x519b, 0x00},
{0x519c, 0x06},
{0x519d, 0x82},
{0x519e, 0x38},
//color matrix (Saturation)
{0x5381, 0x1e},
{0x5382, 0x5b},
{0x5383, 0x08},
{0x5384, 0x0a},
{0x5385, 0x7e},
{0x5386, 0x88},
{0x5387, 0x7c},
{0x5388, 0x6c},
{0x5389, 0x10},
{0x538a, 0x01},
{0x538b, 0x98},
//CIP control (Sharpness)
{0x5300, 0x10},//sharpness
{0x5301, 0x10},//sharpness
{0x5302, 0x18},//sharpness
{0x5303, 0x19},//sharpness
{0x5304, 0x10},
{0x5305, 0x10},
{0x5306, 0x08},//denoise
{0x5307, 0x16},
{0x5308, 0x40},
{0x5309, 0x10},//sharpness
{0x530a, 0x10},//sharpness
{0x530b, 0x04},//sharpness
{0x530c, 0x06},//sharpness
//GAMMA
{0x5480, 0x01},
{0x5481, 0x00},
{0x5482, 0x1e},
{0x5483, 0x3b},
{0x5484, 0x58},
{0x5485, 0x66},
{0x5486, 0x71},
{0x5487, 0x7d},
{0x5488, 0x83},
{0x5489, 0x8f},
{0x548a, 0x98},
{0x548b, 0xa6},
{0x548c, 0xb8},
{0x548d, 0xca},
{0x548e, 0xd7},
{0x548f, 0xe3},
{0x5490, 0x1d},
//Special Digital Effects (SDE) (UV adjust)
{0x5580, 0x06},//enable brightness and contrast
{0x5583, 0x40},//special_effect
{0x5584, 0x10},//special_effect
{0x5586, 0x20},//contrast
{0x5587, 0x00},//brightness
{0x5588, 0x00},//brightness
{0x5589, 0x10},
{0x558a, 0x00},
{0x558b, 0xf8},
{0x501d, 0x40},// enable manual offset of contrast
//power on
{0x3008, 0x02},
//50Hz
{0x3c00, 0x04},
{REG_DLY, 300},
{REGLIST_TAIL, 0x00}, // tail
};
static const DRAM_ATTR uint16_t sensor_fmt_jpeg[][2] = {
{FORMAT_CTRL, 0x00}, // YUV422
{FORMAT_CTRL00, 0x30}, // YUYV
{0x3002, 0x00},//0x1c to 0x00 !!!
{0x3006, 0xff},//0xc3 to 0xff !!!
{0x471c, 0x50},//0xd0 to 0x50 !!!
{REGLIST_TAIL, 0x00}, // tail
};
static const DRAM_ATTR uint16_t sensor_fmt_raw[][2] = {
{FORMAT_CTRL, 0x03}, // RAW (DPC)
{FORMAT_CTRL00, 0x00}, // RAW
{REGLIST_TAIL, 0x00}
};
static const DRAM_ATTR uint16_t sensor_fmt_grayscale[][2] = {
{FORMAT_CTRL, 0x00}, // YUV422
{FORMAT_CTRL00, 0x10}, // Y8
{REGLIST_TAIL, 0x00}
};
static const DRAM_ATTR uint16_t sensor_fmt_yuv422[][2] = {
{FORMAT_CTRL, 0x00}, // YUV422
{FORMAT_CTRL00, 0x30}, // YUYV
{REGLIST_TAIL, 0x00}
};
static const DRAM_ATTR uint16_t sensor_fmt_rgb565[][2] = {
{FORMAT_CTRL, 0x01}, // RGB
{FORMAT_CTRL00, 0x61}, // RGB565 (BGR)
{REGLIST_TAIL, 0x00}
};
static const DRAM_ATTR uint8_t sensor_saturation_levels[9][11] = {
{0x1d, 0x60, 0x03, 0x07, 0x48, 0x4f, 0x4b, 0x40, 0x0b, 0x01, 0x98},//-4
{0x1d, 0x60, 0x03, 0x08, 0x54, 0x5c, 0x58, 0x4b, 0x0d, 0x01, 0x98},//-3
{0x1d, 0x60, 0x03, 0x0a, 0x60, 0x6a, 0x64, 0x56, 0x0e, 0x01, 0x98},//-2
{0x1d, 0x60, 0x03, 0x0b, 0x6c, 0x77, 0x70, 0x60, 0x10, 0x01, 0x98},//-1
{0x1d, 0x60, 0x03, 0x0c, 0x78, 0x84, 0x7d, 0x6b, 0x12, 0x01, 0x98},//0
{0x1d, 0x60, 0x03, 0x0d, 0x84, 0x91, 0x8a, 0x76, 0x14, 0x01, 0x98},//+1
{0x1d, 0x60, 0x03, 0x0e, 0x90, 0x9e, 0x96, 0x80, 0x16, 0x01, 0x98},//+2
{0x1d, 0x60, 0x03, 0x10, 0x9c, 0xac, 0xa2, 0x8b, 0x17, 0x01, 0x98},//+3
{0x1d, 0x60, 0x03, 0x11, 0xa8, 0xb9, 0xaf, 0x96, 0x19, 0x01, 0x98},//+4
};
static const DRAM_ATTR uint8_t sensor_special_effects[7][4] = {
{0x06, 0x40, 0x2c, 0x08},//Normal
{0x46, 0x40, 0x28, 0x08},//Negative
{0x1e, 0x80, 0x80, 0x08},//Grayscale
{0x1e, 0x80, 0xc0, 0x08},//Red Tint
{0x1e, 0x60, 0x60, 0x08},//Green Tint
{0x1e, 0xa0, 0x40, 0x08},//Blue Tint
{0x1e, 0x40, 0xa0, 0x08},//Sepia
};
static const DRAM_ATTR uint16_t sensor_regs_gamma0[][2] = {
{0x5480, 0x01},
{0x5481, 0x08},
{0x5482, 0x14},
{0x5483, 0x28},
{0x5484, 0x51},
{0x5485, 0x65},
{0x5486, 0x71},
{0x5487, 0x7d},
{0x5488, 0x87},
{0x5489, 0x91},
{0x548a, 0x9a},
{0x548b, 0xaa},
{0x548c, 0xb8},
{0x548d, 0xcd},
{0x548e, 0xdd},
{0x548f, 0xea},
{0x5490, 0x1d}
};
static const DRAM_ATTR uint16_t sensor_regs_gamma1[][2] = {
{0x5480, 0x1},
{0x5481, 0x0},
{0x5482, 0x1e},
{0x5483, 0x3b},
{0x5484, 0x58},
{0x5485, 0x66},
{0x5486, 0x71},
{0x5487, 0x7d},
{0x5488, 0x83},
{0x5489, 0x8f},
{0x548a, 0x98},
{0x548b, 0xa6},
{0x548c, 0xb8},
{0x548d, 0xca},
{0x548e, 0xd7},
{0x548f, 0xe3},
{0x5490, 0x1d}
};
static const DRAM_ATTR uint16_t sensor_regs_awb0[][2] = {
{0x5180, 0xff},
{0x5181, 0xf2},
{0x5182, 0x00},
{0x5183, 0x14},
{0x5184, 0x25},
{0x5185, 0x24},
{0x5186, 0x09},
{0x5187, 0x09},
{0x5188, 0x09},
{0x5189, 0x75},
{0x518a, 0x54},
{0x518b, 0xe0},
{0x518c, 0xb2},
{0x518d, 0x42},
{0x518e, 0x3d},
{0x518f, 0x56},
{0x5190, 0x46},
{0x5191, 0xf8},
{0x5192, 0x04},
{0x5193, 0x70},
{0x5194, 0xf0},
{0x5195, 0xf0},
{0x5196, 0x03},
{0x5197, 0x01},
{0x5198, 0x04},
{0x5199, 0x12},
{0x519a, 0x04},
{0x519b, 0x00},
{0x519c, 0x06},
{0x519d, 0x82},
{0x519e, 0x38}
};
#endif

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/*
* This file is part of the OpenMV project.
* author: Juan Schiavoni <juanjoseschiavoni@hotmail.com>
* This work is licensed under the MIT license, see the file LICENSE for details.
*
* OV7670 driver.
*
*/
#ifndef __OV7670_H__
#define __OV7670_H__
#include "sensor.h"
int ov7670_init(sensor_t *sensor);
#endif // __OV7670_H__

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code/components/esp32-camera-master/sensors/private_include/ov7670_regs.h Normal file
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/*
* This file is for the OpenMV project so the OV7670 can be used
* author: Juan Schiavoni <juanjoseschiavoni@hotmail.com>
*
* OV7670 register definitions.
*/
#ifndef __OV7670_REG_REGS_H__
#define __OV7670_REG_REGS_H__
#define GAIN 0x00 /* AGC – Gain control gain setting */
#define BLUE 0x01 /* AWB – Blue channel gain setting */
#define RED 0x02 /* AWB – Red channel gain setting */
#define VREF 0x03 /* AWB – Green channel gain setting */
#define COM1 0x04 /* Common Control 1 */
#define BAVG 0x05 /* U/B Average Level */
#define GAVG 0x06 /* Y/Gb Average Level */
#define AECH 0x07 /* Exposure VAlue - AEC MSB 5 bits */
#define RAVG 0x08 /* V/R Average Level */
#define COM2 0x09 /* Common Control 2 */
#define COM2_SOFT_SLEEP 0x10 /* Soft sleep mode */
#define COM2_OUT_DRIVE_1x 0x00 /* Output drive capability 1x */
#define COM2_OUT_DRIVE_2x 0x01 /* Output drive capability 2x */
#define COM2_OUT_DRIVE_3x 0x02 /* Output drive capability 3x */
#define COM2_OUT_DRIVE_4x 0x03 /* Output drive capability 4x */
#define REG_PID 0x0A /* Product ID Number MSB */
#define REG_VER 0x0B /* Product ID Number LSB */
#define COM3 0x0C /* Common Control 3 */
#define COM3_SWAP_OUT 0x40 /* Output data MSB/LSB swap */
#define COM3_TRI_CLK 0x20 /* Tri-state output clock */
#define COM3_TRI_DATA 0x10 /* Tri-state option output */
#define COM3_SCALE_EN 0x08 /* Scale enable */
#define COM3_DCW 0x04 /* DCW enable */
#define COM4 0x0D /* Common Control 4 */
#define COM4_PLL_BYPASS 0x00 /* Bypass PLL */
#define COM4_PLL_4x 0x40 /* PLL frequency 4x */
#define COM4_PLL_6x 0x80 /* PLL frequency 6x */
#define COM4_PLL_8x 0xc0 /* PLL frequency 8x */
#define COM4_AEC_FULL 0x00 /* AEC evaluate full window */
#define COM4_AEC_1_2 0x10 /* AEC evaluate 1/2 window */
#define COM4_AEC_1_4 0x20 /* AEC evaluate 1/4 window */
#define COM4_AEC_2_3 0x30 /* AEC evaluate 2/3 window */
#define COM5 0x0E /* Common Control 5 */
#define COM5_AFR 0x80 /* Auto frame rate control ON/OFF selection (night mode) */
#define COM5_AFR_SPEED 0x40 /* Auto frame rate control speed selection */
#define COM5_AFR_0 0x00 /* No reduction of frame rate */
#define COM5_AFR_1_2 0x10 /* Max reduction to 1/2 frame rate */
#define COM5_AFR_1_4 0x20 /* Max reduction to 1/4 frame rate */
#define COM5_AFR_1_8 0x30 /* Max reduction to 1/8 frame rate */
#define COM5_AFR_4x 0x04 /* Add frame when AGC reaches 4x gain */
#define COM5_AFR_8x 0x08 /* Add frame when AGC reaches 8x gain */
#define COM5_AFR_16x 0x0c /* Add frame when AGC reaches 16x gain */
#define COM5_AEC_NO_LIMIT 0x01 /* No limit to AEC increase step */
#define COM6 0x0F /* Common Control 6 */
#define COM6_AUTO_WINDOW 0x01 /* Auto window setting ON/OFF selection when format changes */
#define AEC 0x10 /* AEC[7:0] (see register AECH for AEC[15:8]) */
#define CLKRC 0x11 /* Internal Clock */
#define COM7 0x12 /* Common Control 7 */
#define COM7_RESET 0x80 /* SCCB Register Reset */
#define COM7_RES_VGA 0x00 /* Resolution VGA */
#define COM7_RES_QVGA 0x40 /* Resolution QVGA */
#define COM7_BT656 0x20 /* BT.656 protocol ON/OFF */
#define COM7_SENSOR_RAW 0x10 /* Sensor RAW */
#define COM7_FMT_GBR422 0x00 /* RGB output format GBR422 */
#define COM7_FMT_RGB565 0x04 /* RGB output format RGB565 */
#define COM7_FMT_RGB555 0x08 /* RGB output format RGB555 */
#define COM7_FMT_RGB444 0x0C /* RGB output format RGB444 */
#define COM7_FMT_YUV 0x00 /* Output format YUV */
#define COM7_FMT_P_BAYER 0x01 /* Output format Processed Bayer RAW */
#define COM7_FMT_RGB 0x04 /* Output format RGB */
#define COM7_FMT_R_BAYER 0x03 /* Output format Bayer RAW */
#define COM7_SET_FMT(r, x) ((r&0xFC)|((x&0x5)<<0))
#define COM8 0x13 /* Common Control 8 */
#define COM8_FAST_AUTO 0x80 /* Enable fast AGC/AEC algorithm */
#define COM8_STEP_VSYNC 0x00 /* AEC - Step size limited to vertical blank */
#define COM8_STEP_UNLIMIT 0x40 /* AEC - Step size unlimited step size */
#define COM8_BANDF_EN 0x20 /* Banding filter ON/OFF */
#define COM8_AEC_BANDF 0x10 /* Enable AEC below banding value */
#define COM8_AEC_FINE_EN 0x08 /* Fine AEC ON/OFF control */
#define COM8_AGC_EN 0x04 /* AGC Enable */
#define COM8_AWB_EN 0x02 /* AWB Enable */
#define COM8_AEC_EN 0x01 /* AEC Enable */
#define COM8_SET_AGC(r, x) ((r&0xFB)|((x&0x1)<<2))
#define COM8_SET_AWB(r, x) ((r&0xFD)|((x&0x1)<<1))
#define COM8_SET_AEC(r, x) ((r&0xFE)|((x&0x1)<<0))
#define COM9 0x14 /* Common Control 9 */
#define COM9_HISTO_AVG 0x80 /* Histogram or average based AEC/AGC selection */
#define COM9_AGC_GAIN_2x 0x00 /* Automatic Gain Ceiling 2x */
#define COM9_AGC_GAIN_4x 0x10 /* Automatic Gain Ceiling 4x */
#define COM9_AGC_GAIN_8x 0x20 /* Automatic Gain Ceiling 8x */
#define COM9_AGC_GAIN_16x 0x30 /* Automatic Gain Ceiling 16x */
#define COM9_AGC_GAIN_32x 0x40 /* Automatic Gain Ceiling 32x */
#define COM9_DROP_VSYNC 0x04 /* Drop VSYNC output of corrupt frame */
#define COM9_DROP_HREF 0x02 /* Drop HREF output of corrupt frame */
#define COM9_SET_AGC(r, x) ((r&0x8F)|((x&0x07)<<4))
#define COM10 0x15 /* Common Control 10 */
#define COM10_NEGATIVE 0x80 /* Output negative data */
#define COM10_HSYNC_EN 0x40 /* HREF changes to HSYNC */
#define COM10_PCLK_FREE 0x00 /* PCLK output option: free running PCLK */
#define COM10_PCLK_MASK 0x20 /* PCLK output option: masked during horizontal blank */
#define COM10_PCLK_REV 0x10 /* PCLK reverse */
#define COM10_HREF_REV 0x08 /* HREF reverse */
#define COM10_VSYNC_FALLING 0x00 /* VSYNC changes on falling edge of PCLK */
#define COM10_VSYNC_RISING 0x04 /* VSYNC changes on rising edge of PCLK */
#define COM10_VSYNC_NEG 0x02 /* VSYNC negative */
#define COM10_OUT_RANGE_8 0x01 /* Output data range: Full range */
#define COM10_OUT_RANGE_10 0x00 /* Output data range: Data from [10] to [F0] (8 MSBs) */
#define RSVD_16 0x16 /* Reserved register */
#define HSTART 0x17 /* Horizontal Frame (HREF column) Start high 8-bit(low 3 bits are at HREF[2:0]) */
#define HSTOP 0x18 /* Horizontal Frame (HREF column) end high 8-bit (low 3 bits are at HREF[5:3]) */
#define VSTART 0x19 /* Vertical Frame (row) Start high 8-bit (low 2 bits are at VREF[1:0]) */
#define VSTOP 0x1A /* Vertical Frame (row) End high 8-bit (low 2 bits are at VREF[3:2]) */
#define PSHFT 0x1B /* Data Format - Pixel Delay Select */
#define REG_MIDH 0x1C /* Manufacturer ID Byte – High */
#define REG_MIDL 0x1D /* Manufacturer ID Byte – Low */
#define MVFP 0x1E /* Mirror/Vflip Enable */
#define MVFP_MIRROR 0x20 /* Mirror image */
#define MVFP_FLIP 0x10 /* Vertical flip */
#define MVFP_SUN 0x02 /* Black sun enable */
#define MVFP_SET_MIRROR(r,x) ((r&0xDF)|((x&1)<<5)) /* change only bit5 according to x */
#define MVFP_SET_FLIP(r,x) ((r&0xEF)|((x&1)<<4)) /* change only bit4 according to x */
#define LAEC 0x1F /* Fine AEC Value - defines exposure value less than one row period (Reserved?) */
#define ADCCTR0 0x20 /* ADC control */
#define ADCCTR1 0x21 /* reserved */
#define ADCCTR2 0x22 /* reserved */
#define ADCCTR3 0x23 /* reserved */
#define AEW 0x24 /* AGC/AEC - Stable Operating Region (Upper Limit) */
#define AEB 0x25 /* AGC/AEC - Stable Operating Region (Lower Limit) */
#define VPT 0x26 /* AGC/AEC Fast Mode Operating Region */
#define BBIAS 0x27 /* B channel signal output bias (effective only when COM6[3]=1) */
#define GbBIAS 0x28 /* Gb channel signal output bias (effective only when COM6[3]=1) */
#define RSVD_29 0x29 /* reserved */
#define EXHCH 0x2A /* Dummy Pixel Insert MSB */
#define EXHCL 0x2B /* Dummy Pixel Insert LSB */
#define RBIAS 0x2C /* R channel signal output bias (effective only when COM6[3]=1) */
#define ADVFL 0x2D /* LSB of Insert Dummy Rows in Vertical Sync (1 bit equals 1 row) */
#define ADVFH 0x2E /* MSB of Insert Dummy Rows in Vertical Sync */
#define YAVE 0x2F /* Y/G Channel Average Value */
#define HSYST 0x30 /* HSync rising edge delay */
#define HSYEN 0x31 /* HSync falling edge delay */
#define HREF 0x32 /* Image Start and Size Control DIFFERENT CONTROL SEQUENCE */
#define CHLF 0x33 /* Array Current control */
#define ARBLM 0x34 /* Array reference control */
#define RSVD_35 0x35 /* Reserved */
#define RSVD_36 0x36 /* Reserved */
#define ADC 0x37 /* ADC control */
#define ACOM 0x38 /* ADC and analog common mode control */
#define OFON 0x39 /* ADC offset control */
#define TSLB 0x3A /* Line buffer test option */
#define COM11 0x3B /* Common control 11 */
#define COM11_EXP 0x02
#define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
#define COM12 0x3C /* Common control 12 */
#define COM13 0x3D /* Common control 13 */
#define COM13_GAMMA 0x80 /* Gamma enable */
#define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
#define COM14 0x3E /* Common Control 14 */
#define EDGE 0x3F /* edge enhancement adjustment */
#define COM15 0x40 /* Common Control 15 DIFFERENT CONTROLS */
#define COM15_SET_RGB565(r,x) ((r&0xEF)|((x&1)<<4)) /* set rgb565 mode */
#define COM15_RGB565 0x10 /* RGB565 output */
#define COM15_R00FF 0xC0 /* Output range: [00] to [FF] */
#define COM16 0x41 /* Common Control 16 DIFFERENT CONTROLS */
#define COM16_AWBGAIN 0x08 /* AWB gain enable */
#define COM17 0x42 /* Common Control 17 */
#define AWBC1 0x43 /* Reserved */
#define AWBC2 0x44 /* Reserved */
#define AWBC3 0x45 /* Reserved */
#define AWBC4 0x46 /* Reserved */
#define AWBC5 0x47 /* Reserved */
#define AWBC6 0x48 /* Reserved */
#define RSVD_49 0x49 /* Reserved */
#define RSVD_4A 0x4A /* Reserved */
#define REG4B 0x4B /* Register 4B */
#define DNSTH 0x4C /* Denoise strength */
#define RSVD_4D 0x4D /* Reserved */
#define RSVD_4E 0x4E /* Reserved */
#define MTX1 0x4F /* Matrix coefficient 1 */
#define MTX2 0x50 /* Matrix coefficient 2 */
#define MTX3 0x51 /* Matrix coefficient 3 */
#define MTX4 0x52 /* Matrix coefficient 4 */
#define MTX5 0x53 /* Matrix coefficient 5 */
#define MTX6 0x54 /* Matrix coefficient 6 */
#define BRIGHTNESS 0x55 /* Brightness control */
#define CONTRAST 0x56 /* Contrast control */
#define CONTRASCENTER 0x57 /* Contrast center */
#define MTXS 0x58 /* Matrix coefficient sign for coefficient 5 to 0*/
#define RSVD_59 0x59 /* Reserved */
#define RSVD_5A 0x5A /* Reserved */
#define RSVD_5B 0x5B /* Reserved */
#define RSVD_5C 0x5C /* Reserved */
#define RSVD_5D 0x5D /* Reserved */
#define RSVD_5E 0x5E /* Reserved */
#define RSVD_5F 0x5F /* Reserved */
#define RSVD_60 0x60 /* Reserved */
#define RSVD_61 0x61 /* Reserved */
#define LCC1 0x62 /* Lens correction option 1 */
#define LCC2 0x63 /* Lens correction option 2 */
#define LCC3 0x64 /* Lens correction option 3 */
#define LCC4 0x65 /* Lens correction option 4 */
#define LCC5 0x66 /* Lens correction option 5 */
#define MANU 0x67 /* Manual U Value */
#define MANV 0x68 /* Manual V Value */
#define GFIX 0x69 /* Fix gain control */
#define GGAIN 0x6A /* G channel AWB gain */
#define DBLV 0x6B /* PLL and clock ? */
#define AWBCTR3 0x6C /* AWB Control 3 */
#define AWBCTR2 0x6D /* AWB Control 2 */
#define AWBCTR1 0x6E /* AWB Control 1 */
#define AWBCTR0 0x6F /* AWB Control 0 */
#define SCALING_XSC 0x70 /* test pattern and horizontal scaling factor */
#define SCALING_XSC_CBAR(r) (r&0x7F) /* make sure bit7 is 0 for color bar */
#define SCALING_YSC 0x71 /* test pattern and vertical scaling factor */
#define SCALING_YSC_CBAR(r,x) ((r&0x7F)|((x&1)<<7)) /* change bit7 for color bar on/off */
#define SCALING_DCWCTR 0x72 /* DCW control */
#define SCALING_PCLK_DIV 0x73 /* */
#define REG74 0x74 /* */
#define REG75 0x75 /* */
#define REG76 0x76 /* */
#define REG77 0x77 /* */
#define RSVD_78 0x78 /* Reserved */
#define RSVD_79 0x79 /* Reserved */
#define SLOP 0x7A /* Gamma curve highest segment slope */
#define GAM1 0x7B /* Gamma Curve 1st Segment Input End Point 0x04 Output Value */
#define GAM2 0x7C /* Gamma Curve 2nd Segment Input End Point 0x08 Output Value */
#define GAM3 0x7D /* Gamma Curve 3rd Segment Input End Point 0x10 Output Value */
#define GAM4 0x7E /* Gamma Curve 4th Segment Input End Point 0x20 Output Value */
#define GAM5 0x7F /* Gamma Curve 5th Segment Input End Point 0x28 Output Value */
#define GAM6 0x80 /* Gamma Curve 6rd Segment Input End Point 0x30 Output Value */
#define GAM7 0x81 /* Gamma Curve 7th Segment Input End Point 0x38 Output Value */
#define GAM8 0x82 /* Gamma Curve 8th Segment Input End Point 0x40 Output Value */
#define GAM9 0x83 /* Gamma Curve 9th Segment Input End Point 0x48 Output Value */
#define GAM10 0x84 /* Gamma Curve 10th Segment Input End Point 0x50 Output Value */
#define GAM11 0x85 /* Gamma Curve 11th Segment Input End Point 0x60 Output Value */
#define GAM12 0x86 /* Gamma Curve 12th Segment Input End Point 0x70 Output Value */
#define GAM13 0x87 /* Gamma Curve 13th Segment Input End Point 0x90 Output Value */
#define GAM14 0x88 /* Gamma Curve 14th Segment Input End Point 0xB0 Output Value */
#define GAM15 0x89 /* Gamma Curve 15th Segment Input End Point 0xD0 Output Value */
#define RSVD_8A 0x8A /* Reserved */
#define RSVD_8B 0x8B /* Reserved */
#define RGB444 0x8C /* */
#define RSVD_8D 0x8D /* Reserved */
#define RSVD_8E 0x8E /* Reserved */
#define RSVD_8F 0x8F /* Reserved */
#define RSVD_90 0x90 /* Reserved */
#define RSVD_91 0x91 /* Reserved */
#define DM_LNL 0x92 /* Dummy line low 8 bit */
#define DM_LNH 0x93 /* Dummy line high 8 bit */
#define LCC6 0x94 /* Lens correction option 6 */
#define LCC7 0x95 /* Lens correction option 7 */
#define RSVD_96 0x96 /* Reserved */
#define RSVD_97 0x97 /* Reserved */
#define RSVD_98 0x98 /* Reserved */
#define RSVD_99 0x99 /* Reserved */
#define RSVD_9A 0x9A /* Reserved */
#define RSVD_9B 0x9B /* Reserved */
#define RSVD_9C 0x9C /* Reserved */
#define BD50ST 0x9D /* 50 Hz banding filter value */
#define BD60ST 0x9E /* 60 Hz banding filter value */
#define HAECC1 0x9F /* Histogram-based AEC/AGC control 1 */
#define HAECC2 0xA0 /* Histogram-based AEC/AGC control 2 */
#define RSVD_A1 0xA1 /* Reserved */
#define SCALING_PCLK_DELAY 0xA2 /* Pixel clock delay */
#define RSVD_A3 0xA3 /* Reserved */
#define NT_CNTRL 0xA4 /* */
#define BD50MAX 0xA5 /* 50 Hz banding step limit */
#define HAECC3 0xA6 /* Histogram-based AEC/AGC control 3 */
#define HAECC4 0xA7 /* Histogram-based AEC/AGC control 4 */
#define HAECC5 0xA8 /* Histogram-based AEC/AGC control 5 */
#define HAECC6 0xA9 /* Histogram-based AEC/AGC control 6 */
#define HAECC7 0xAA /* Histogram-based AEC/AGC control 7 */
#define HAECC_EN 0x80 /* Histogram-based AEC algorithm enable */
#define BD60MAX 0xAB /* 60 Hz banding step limit */
#define STR_OPT 0xAC /* Register AC */
#define STR_R 0xAD /* R gain for led output frame */
#define STR_G 0xAE /* G gain for led output frame */
#define STR_B 0xAF /* B gain for led output frame */
#define RSVD_B0 0xB0 /* Reserved */
#define ABLC1 0xB1 /* */
#define RSVD_B2 0xB2 /* Reserved */
#define THL_ST 0xB3 /* ABLC target */
#define THL_DLT 0xB5 /* ABLC stable range */
#define RSVD_B6 0xB6 /* Reserved */
#define RSVD_B7 0xB7 /* Reserved */
#define RSVD_B8 0xB8 /* Reserved */
#define RSVD_B9 0xB9 /* Reserved */
#define RSVD_BA 0xBA /* Reserved */
#define RSVD_BB 0xBB /* Reserved */
#define RSVD_BC 0xBC /* Reserved */
#define RSVD_BD 0xBD /* Reserved */
#define AD_CHB 0xBE /* blue channel black level compensation */
#define AD_CHR 0xBF /* Red channel black level compensation */
#define AD_CHGb 0xC0 /* Gb channel black level compensation */
#define AD_CHGr 0xC1 /* Gr channel black level compensation */
#define RSVD_C2 0xC2 /* Reserved */
#define RSVD_C3 0xC3 /* Reserved */
#define RSVD_C4 0xC4 /* Reserved */
#define RSVD_C5 0xC5 /* Reserved */
#define RSVD_C6 0xC6 /* Reserved */
#define RSVD_C7 0xC7 /* Reserved */
#define RSVD_C8 0xC8 /* Reserved */
#define SATCTR 0xC9 /* Saturation control */
#define SET_REG(reg, x) (##reg_DEFAULT|x)
#endif //__OV7670_REG_REGS_H__

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/*
* This file is part of the OpenMV project.
* Copyright (c) 2013/2014 Ibrahim Abdelkader <i.abdalkader@gmail.com>
* This work is licensed under the MIT license, see the file LICENSE for details.
*
* OV7725 driver.
*
*/
#ifndef __OV7725_H__
#define __OV7725_H__
#include "sensor.h"
int ov7725_init(sensor_t *sensor);
#endif // __OV7725_H__

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/*
* This file is part of the OpenMV project.
* Copyright (c) 2013/2014 Ibrahim Abdelkader <i.abdalkader@gmail.com>
* This work is licensed under the MIT license, see the file LICENSE for details.
*
* OV2640 register definitions.
*/
#ifndef __REG_REGS_H__
#define __REG_REGS_H__
#define GAIN 0x00 /* AGC – Gain control gain setting */
#define BLUE 0x01 /* AWB – Blue channel gain setting */
#define RED 0x02 /* AWB – Red channel gain setting */
#define GREEN 0x03 /* AWB – Green channel gain setting */
#define BAVG 0x05 /* U/B Average Level */
#define GAVG 0x06 /* Y/Gb Average Level */
#define RAVG 0x07 /* V/R Average Level */
#define AECH 0x08 /* Exposure Value – AEC MSBs */
#define COM2 0x09 /* Common Control 2 */
#define COM2_SOFT_SLEEP 0x10 /* Soft sleep mode */
#define COM2_OUT_DRIVE_1x 0x00 /* Output drive capability 1x */
#define COM2_OUT_DRIVE_2x 0x01 /* Output drive capability 2x */
#define COM2_OUT_DRIVE_3x 0x02 /* Output drive capability 3x */
#define COM2_OUT_DRIVE_4x 0x03 /* Output drive capability 4x */
#define REG_PID 0x0A /* Product ID Number MSB */
#define REG_VER 0x0B /* Product ID Number LSB */
#define COM3 0x0C /* Common Control 3 */
#define COM3_VFLIP 0x80 /* Vertical flip image ON/OFF selection */
#define COM3_MIRROR 0x40 /* Horizontal mirror image ON/OFF selection */
#define COM3_SWAP_BR 0x20 /* Swap B/R output sequence in RGB output mode */
#define COM3_SWAP_YUV 0x10 /* Swap Y/UV output sequence in YUV output mode */
#define COM3_SWAP_MSB 0x08 /* Swap output MSB/LSB */
#define COM3_TRI_CLOCK 0x04 /* Tri-state option for output clock at power-down period */
#define COM3_TRI_DATA 0x02 /* Tri-state option for output data at power-down period */
#define COM3_COLOR_BAR 0x01 /* Sensor color bar test pattern output enable */
#define COM3_SET_CBAR(r, x) ((r&0xFE)|((x&1)<<0))
#define COM3_SET_MIRROR(r, x) ((r&0xBF)|((x&1)<<6))
#define COM3_SET_FLIP(r, x) ((r&0x7F)|((x&1)<<7))
#define COM4 0x0D /* Common Control 4 */
#define COM4_PLL_BYPASS 0x00 /* Bypass PLL */
#define COM4_PLL_4x 0x40 /* PLL frequency 4x */
#define COM4_PLL_6x 0x80 /* PLL frequency 6x */
#define COM4_PLL_8x 0xc0 /* PLL frequency 8x */
#define COM4_AEC_FULL 0x00 /* AEC evaluate full window */
#define COM4_AEC_1_2 0x10 /* AEC evaluate 1/2 window */
#define COM4_AEC_1_4 0x20 /* AEC evaluate 1/4 window */
#define COM4_AEC_2_3 0x30 /* AEC evaluate 2/3 window */
#define COM5 0x0E /* Common Control 5 */
#define COM5_AFR 0x80 /* Auto frame rate control ON/OFF selection (night mode) */
#define COM5_AFR_SPEED 0x40 /* Auto frame rate control speed selection */
#define COM5_AFR_0 0x00 /* No reduction of frame rate */
#define COM5_AFR_1_2 0x10 /* Max reduction to 1/2 frame rate */
#define COM5_AFR_1_4 0x20 /* Max reduction to 1/4 frame rate */
#define COM5_AFR_1_8 0x30 /* Max reduction to 1/8 frame rate */
#define COM5_AFR_4x 0x04 /* Add frame when AGC reaches 4x gain */
#define COM5_AFR_8x 0x08 /* Add frame when AGC reaches 8x gain */
#define COM5_AFR_16x 0x0c /* Add frame when AGC reaches 16x gain */
#define COM5_AEC_NO_LIMIT 0x01 /* No limit to AEC increase step */
#define COM6 0x0F /* Common Control 6 */
#define COM6_AUTO_WINDOW 0x01 /* Auto window setting ON/OFF selection when format changes */
#define AEC 0x10 /* AEC[7:0] (see register AECH for AEC[15:8]) */
#define CLKRC 0x11 /* Internal Clock */
#define COM7 0x12 /* Common Control 7 */
#define COM7_RESET 0x80 /* SCCB Register Reset */
#define COM7_RES_VGA 0x00 /* Resolution VGA */
#define COM7_RES_QVGA 0x40 /* Resolution QVGA */
#define COM7_BT656 0x20 /* BT.656 protocol ON/OFF */
#define COM7_SENSOR_RAW 0x10 /* Sensor RAW */
#define COM7_FMT_GBR422 0x00 /* RGB output format GBR422 */
#define COM7_FMT_RGB565 0x04 /* RGB output format RGB565 */
#define COM7_FMT_RGB555 0x08 /* RGB output format RGB555 */
#define COM7_FMT_RGB444 0x0C /* RGB output format RGB444 */
#define COM7_FMT_YUV 0x00 /* Output format YUV */
#define COM7_FMT_P_BAYER 0x01 /* Output format Processed Bayer RAW */
#define COM7_FMT_RGB 0x02 /* Output format RGB */
#define COM7_FMT_R_BAYER 0x03 /* Output format Bayer RAW */
#define COM7_SET_FMT(r, x) ((r&0xFC)|((x&0x3)<<0))
#define COM7_SET_RGB(r, x) ((r&0xF0)|(x&0x0C)|COM7_FMT_RGB)
#define COM8 0x13 /* Common Control 8 */
#define COM8_FAST_AUTO 0x80 /* Enable fast AGC/AEC algorithm */
#define COM8_STEP_VSYNC 0x00 /* AEC - Step size limited to vertical blank */
#define COM8_STEP_UNLIMIT 0x40 /* AEC - Step size unlimited step size */
#define COM8_BANDF_EN 0x20 /* Banding filter ON/OFF */
#define COM8_AEC_BANDF 0x10 /* Enable AEC below banding value */
#define COM8_AEC_FINE_EN 0x08 /* Fine AEC ON/OFF control */
#define COM8_AGC_EN 0x04 /* AGC Enable */
#define COM8_AWB_EN 0x02 /* AWB Enable */
#define COM8_AEC_EN 0x01 /* AEC Enable */
#define COM8_SET_AGC(r, x) ((r&0xFB)|((x&0x1)<<2))
#define COM8_SET_AWB(r, x) ((r&0xFD)|((x&0x1)<<1))
#define COM8_SET_AEC(r, x) ((r&0xFE)|((x&0x1)<<0))
#define COM9 0x14 /* Common Control 9 */
#define COM9_HISTO_AVG 0x80 /* Histogram or average based AEC/AGC selection */
#define COM9_AGC_GAIN_2x 0x00 /* Automatic Gain Ceiling 2x */
#define COM9_AGC_GAIN_4x 0x10 /* Automatic Gain Ceiling 4x */
#define COM9_AGC_GAIN_8x 0x20 /* Automatic Gain Ceiling 8x */
#define COM9_AGC_GAIN_16x 0x30 /* Automatic Gain Ceiling 16x */
#define COM9_AGC_GAIN_32x 0x40 /* Automatic Gain Ceiling 32x */
#define COM9_DROP_VSYNC 0x04 /* Drop VSYNC output of corrupt frame */
#define COM9_DROP_HREF 0x02 /* Drop HREF output of corrupt frame */
#define COM9_SET_AGC(r, x) ((r&0x8F)|((x&0x07)<<4))
#define COM10 0x15 /* Common Control 10 */
#define COM10_NEGATIVE 0x80 /* Output negative data */
#define COM10_HSYNC_EN 0x40 /* HREF changes to HSYNC */
#define COM10_PCLK_FREE 0x00 /* PCLK output option: free running PCLK */
#define COM10_PCLK_MASK 0x20 /* PCLK output option: masked during horizontal blank */
#define COM10_PCLK_REV 0x10 /* PCLK reverse */
#define COM10_HREF_REV 0x08 /* HREF reverse */
#define COM10_VSYNC_FALLING 0x00 /* VSYNC changes on falling edge of PCLK */
#define COM10_VSYNC_RISING 0x04 /* VSYNC changes on rising edge of PCLK */
#define COM10_VSYNC_NEG 0x02 /* VSYNC negative */
#define COM10_OUT_RANGE_8 0x01 /* Output data range: Full range */
#define COM10_OUT_RANGE_10 0x00 /* Output data range: Data from [10] to [F0] (8 MSBs) */
#define REG16 0x16 /* Register 16 */
#define REG16_BIT_SHIFT 0x80 /* Bit shift test pattern options */
#define HSTART 0x17 /* Horizontal Frame (HREF column) Start 8 MSBs (2 LSBs are at HREF[5:4]) */
#define HSIZE 0x18 /* Horizontal Sensor Size (2 LSBs are at HREF[1:0]) */
#define VSTART 0x19 /* Vertical Frame (row) Start 8 MSBs (1 LSB is at HREF[6]) */
#define VSIZE 0x1A /* Vertical Sensor Size (1 LSB is at HREF[2]) */
#define PSHFT 0x1B /* Data Format - Pixel Delay Select */
#define REG_MIDH 0x1C /* Manufacturer ID Byte – High */
#define REG_MIDL 0x1D /* Manufacturer ID Byte – Low */
#define LAEC 0x1F /* Fine AEC Value - defines exposure value less than one row period */
#define COM11 0x20 /* Common Control 11 */
#define COM11_SNGL_FRAME_EN 0x02 /* Single frame ON/OFF selection */
#define COM11_SNGL_XFR_TRIG 0x01 /* Single frame transfer trigger */
#define BDBASE 0x22 /* Banding Filter Minimum AEC Value */
#define DBSTEP 0x23 /* Banding Filter Maximum Step */
#define AEW 0x24 /* AGC/AEC - Stable Operating Region (Upper Limit) */
#define AEB 0x25 /* AGC/AEC - Stable Operating Region (Lower Limit) */
#define VPT 0x26 /* AGC/AEC Fast Mode Operating Region */
#define REG28 0x28 /* Selection on the number of dummy rows, N */
#define HOUTSIZE 0x29 /* Horizontal Data Output Size MSBs (2 LSBs at register EXHCH[1:0]) */
#define EXHCH 0x2A /* Dummy Pixel Insert MSB */
#define EXHCL 0x2B /* Dummy Pixel Insert LSB */
#define VOUTSIZE 0x2C /* Vertical Data Output Size MSBs (LSB at register EXHCH[2]) */
#define ADVFL 0x2D /* LSB of Insert Dummy Rows in Vertical Sync (1 bit equals 1 row) */
#define ADVFH 0x2E /* MSB of Insert Dummy Rows in Vertical Sync */
#define YAVE 0x2F /* Y/G Channel Average Value */
#define LUMHTH 0x30 /* Histogram AEC/AGC Luminance High Level Threshold */
#define LUMLTH 0x31 /* Histogram AEC/AGC Luminance Low Level Threshold */
#define HREF 0x32 /* Image Start and Size Control */
#define DM_LNL 0x33 /* Dummy Row Low 8 Bits */
#define DM_LNH 0x34 /* Dummy Row High 8 Bits */
#define ADOFF_B 0x35 /* AD Offset Compensation Value for B Channel */
#define ADOFF_R 0x36 /* AD Offset Compensation Value for R Channel */
#define ADOFF_GB 0x37 /* AD Offset Compensation Value for GB Channel */
#define ADOFF_GR 0x38 /* AD Offset Compensation Value for GR Channel */
#define OFF_B 0x39 /* AD Offset Compensation Value for B Channel */
#define OFF_R 0x3A /* AD Offset Compensation Value for R Channel */
#define OFF_GB 0x3B /* AD Offset Compensation Value for GB Channel */
#define OFF_GR 0x3C /* AD Offset Compensation Value for GR Channel */
#define COM12 0x3D /* DC offset compensation for analog process */
#define COM13 0x3E /* Common Control 13 */
#define COM13_BLC_EN 0x80 /* BLC enable */
#define COM13_ADC_EN 0x40 /* ADC channel BLC ON/OFF control */
#define COM13_ANALOG_BLC 0x20 /* Analog processing channel BLC ON/OFF control */
#define COM13_ABLC_GAIN_EN 0x04 /* ABLC gain trigger enable */
#define COM14 0x3F /* Common Control 14 */
#define COM15 0x40 /* Common Control 15 */
#define COM16 0x41 /* Common Control 16 */
#define TGT_B 0x42 /* BLC Blue Channel Target Value */
#define TGT_R 0x43 /* BLC Red Channel Target Value */
#define TGT_GB 0x44 /* BLC Gb Channel Target Value */
#define TGT_GR 0x45 /* BLC Gr Channel Target Value */
#define LC_CTR 0x46 /* Lens Correction Control */
#define LC_CTR_RGB_COMP_1 0x00 /* R, G, and B channel compensation coefficient is set by LC_COEF (0x49) */
#define LC_CTR_RGB_COMP_3 0x04 /* R, G, and B channel compensation coefficient is set by registers
LC_COEFB (0x4B), LC_COEF (0x49), and LC_COEFR (0x4C), respectively */
#define LC_CTR_EN 0x01 /* Lens correction enable */
#define LC_XC 0x47 /* X Coordinate of Lens Correction Center Relative to Array Center */
#define LC_YC 0x48 /* Y Coordinate of Lens Correction Center Relative to Array Center */
#define LC_COEF 0x49 /* Lens Correction Coefficient */
#define LC_RADI 0x4A /* Lens Correction Radius */
#define LC_COEFB 0x4B /* Lens Correction B Channel Compensation Coefficient */
#define LC_COEFR 0x4C /* Lens Correction R Channel Compensation Coefficient */
#define FIXGAIN 0x4D /* Analog Fix Gain Amplifier */
#define AREF0 0x4E /* Sensor Reference Control */
#define AREF1 0x4F /* Sensor Reference Current Control */
#define AREF2 0x50 /* Analog Reference Control */
#define AREF3 0x51 /* ADC Reference Control */
#define AREF4 0x52 /* ADC Reference Control */
#define AREF5 0x53 /* ADC Reference Control */
#define AREF6 0x54 /* Analog Reference Control */
#define AREF7 0x55 /* Analog Reference Control */
#define UFIX 0x60 /* U Channel Fixed Value Output */
#define VFIX 0x61 /* V Channel Fixed Value Output */
#define AWBB_BLK 0x62 /* AWB Option for Advanced AWB */
#define AWB_CTRL0 0x63 /* AWB Control Byte 0 */
#define AWB_CTRL0_GAIN_EN 0x80 /* AWB gain enable */
#define AWB_CTRL0_CALC_EN 0x40 /* AWB calculate enable */
#define AWB_CTRL0_WBC_MASK 0x0F /* WBC threshold 2 */
#define DSP_CTRL1 0x64 /* DSP Control Byte 1 */
#define DSP_CTRL1_FIFO_EN 0x80 /* FIFO enable/disable selection */
#define DSP_CTRL1_UV_EN 0x40 /* UV adjust function ON/OFF selection */
#define DSP_CTRL1_SDE_EN 0x20 /* SDE enable */
#define DSP_CTRL1_MTRX_EN 0x10 /* Color matrix ON/OFF selection */
#define DSP_CTRL1_INTRP_EN 0x08 /* Interpolation ON/OFF selection */
#define DSP_CTRL1_GAMMA_EN 0x04 /* Gamma function ON/OFF selection */
#define DSP_CTRL1_BLACK_EN 0x02 /* Black defect auto correction ON/OFF */
#define DSP_CTRL1_WHITE_EN 0x01 /* White defect auto correction ON/OFF */
#define DSP_CTRL2 0x65 /* DSP Control Byte 2 */
#define DSP_CTRL2_VDCW_EN 0x08 /* Vertical DCW enable */
#define DSP_CTRL2_HDCW_EN 0x04 /* Horizontal DCW enable */
#define DSP_CTRL2_VZOOM_EN 0x02 /* Vertical zoom out enable */
#define DSP_CTRL2_HZOOM_EN 0x01 /* Horizontal zoom out enable */
#define DSP_CTRL3 0x66 /* DSP Control Byte 3 */
#define DSP_CTRL3_UV_EN 0x80 /* UV output sequence option */
#define DSP_CTRL3_CBAR_EN 0x20 /* DSP color bar ON/OFF selection */
#define DSP_CTRL3_FIFO_EN 0x08 /* FIFO power down ON/OFF selection */
#define DSP_CTRL3_SCAL1_PWDN 0x04 /* Scaling module power down control 1 */
#define DSP_CTRL3_SCAL2_PWDN 0x02 /* Scaling module power down control 2 */
#define DSP_CTRL3_INTRP_PWDN 0x01 /* Interpolation module power down control */
#define DSP_CTRL3_SET_CBAR(r, x) ((r&0xDF)|((x&1)<<5))
#define DSP_CTRL4 0x67 /* DSP Control Byte 4 */
#define DSP_CTRL4_YUV_RGB 0x00 /* Output selection YUV or RGB */
#define DSP_CTRL4_RAW8 0x02 /* Output selection RAW8 */
#define DSP_CTRL4_RAW10 0x03 /* Output selection RAW10 */
#define AWB_BIAS 0x68 /* AWB BLC Level Clip */
#define AWB_CTRL1 0x69 /* AWB Control 1 */
#define AWB_CTRL2 0x6A /* AWB Control 2 */
#define AWB_CTRL3 0x6B /* AWB Control 3 */
#define AWB_CTRL3_ADVANCED 0x80 /* AWB mode select - Advanced AWB */
#define AWB_CTRL3_SIMPLE 0x00 /* AWB mode select - Simple AWB */
#define AWB_CTRL4 0x6C /* AWB Control 4 */
#define AWB_CTRL5 0x6D /* AWB Control 5 */
#define AWB_CTRL6 0x6E /* AWB Control 6 */
#define AWB_CTRL7 0x6F /* AWB Control 7 */
#define AWB_CTRL8 0x70 /* AWB Control 8 */
#define AWB_CTRL9 0x71 /* AWB Control 9 */
#define AWB_CTRL10 0x72 /* AWB Control 10 */
#define AWB_CTRL11 0x73 /* AWB Control 11 */
#define AWB_CTRL12 0x74 /* AWB Control 12 */
#define AWB_CTRL13 0x75 /* AWB Control 13 */
#define AWB_CTRL14 0x76 /* AWB Control 14 */
#define AWB_CTRL15 0x77 /* AWB Control 15 */
#define AWB_CTRL16 0x78 /* AWB Control 16 */
#define AWB_CTRL17 0x79 /* AWB Control 17 */
#define AWB_CTRL18 0x7A /* AWB Control 18 */
#define AWB_CTRL19 0x7B /* AWB Control 19 */
#define AWB_CTRL20 0x7C /* AWB Control 20 */
#define AWB_CTRL21 0x7D /* AWB Control 21 */
#define GAM1 0x7E /* Gamma Curve 1st Segment Input End Point 0x04 Output Value */
#define GAM2 0x7F /* Gamma Curve 2nd Segment Input End Point 0x08 Output Value */
#define GAM3 0x80 /* Gamma Curve 3rd Segment Input End Point 0x10 Output Value */
#define GAM4 0x81 /* Gamma Curve 4th Segment Input End Point 0x20 Output Value */
#define GAM5 0x82 /* Gamma Curve 5th Segment Input End Point 0x28 Output Value */
#define GAM6 0x83 /* Gamma Curve 6th Segment Input End Point 0x30 Output Value */
#define GAM7 0x84 /* Gamma Curve 7th Segment Input End Point 0x38 Output Value */
#define GAM8 0x85 /* Gamma Curve 8th Segment Input End Point 0x40 Output Value */
#define GAM9 0x86 /* Gamma Curve 9th Segment Input End Point 0x48 Output Value */
#define GAM10 0x87 /* Gamma Curve 10th Segment Input End Point 0x50 Output Value */
#define GAM11 0x88 /* Gamma Curve 11th Segment Input End Point 0x60 Output Value */
#define GAM12 0x89 /* Gamma Curve 12th Segment Input End Point 0x70 Output Value */
#define GAM13 0x8A /* Gamma Curve 13th Segment Input End Point 0x90 Output Value */
#define GAM14 0x8B /* Gamma Curve 14th Segment Input End Point 0xB0 Output Value */
#define GAM15 0x8C /* Gamma Curve 15th Segment Input End Point 0xD0 Output Value */
#define SLOP 0x8D /* Gamma Curve Highest Segment Slope */
#define DNSTH 0x8E /* De-noise Threshold */
#define EDGE0 0x8F /* Edge Enhancement Strength Control */
#define EDGE1 0x90 /* Edge Enhancement Threshold Control */
#define DNSOFF 0x91 /* Auto De-noise Threshold Control */
#define EDGE2 0x92 /* Edge Enhancement Strength Upper Limit */
#define EDGE3 0x93 /* Edge Enhancement Strength Upper Limit */
#define MTX1 0x94 /* Matrix Coefficient 1 */
#define MTX2 0x95 /* Matrix Coefficient 2 */
#define MTX3 0x96 /* Matrix Coefficient 3 */
#define MTX4 0x97 /* Matrix Coefficient 4 */
#define MTX5 0x98 /* Matrix Coefficient 5 */
#define MTX6 0x99 /* Matrix Coefficient 6 */
#define MTX_CTRL 0x9A /* Matrix Control */
#define MTX_CTRL_DBL_EN 0x80 /* Matrix double ON/OFF selection */
#define BRIGHTNESS 0x9B /* Brightness Control */
#define CONTRAST 0x9C /* Contrast Gain */
#define UVADJ0 0x9E /* Auto UV Adjust Control 0 */
#define UVADJ1 0x9F /* Auto UV Adjust Control 1 */
#define SCAL0 0xA0 /* DCW Ratio Control */
#define SCAL1 0xA1 /* Horizontal Zoom Out Control */
#define SCAL2 0xA2 /* Vertical Zoom Out Control */
#define FIFODLYM 0xA3 /* FIFO Manual Mode Delay Control */
#define FIFODLYA 0xA4 /* FIFO Auto Mode Delay Control */
#define SDE 0xA6 /* Special Digital Effect Control */
#define SDE_NEGATIVE_EN 0x40 /* Negative image enable */
#define SDE_GRAYSCALE_EN 0x20 /* Gray scale image enable */
#define SDE_V_FIXED_EN 0x10 /* V fixed value enable */
#define SDE_U_FIXED_EN 0x08 /* U fixed value enable */
#define SDE_CONT_BRIGHT_EN 0x04 /* Contrast/Brightness enable */
#define SDE_SATURATION_EN 0x02 /* Saturation enable */
#define SDE_HUE_EN 0x01 /* Hue enable */
#define USAT 0xA7 /* U Component Saturation Gain */
#define VSAT 0xA8 /* V Component Saturation Gain */
#define HUECOS 0xA9 /* Cosine value × 0x80 */
#define HUESIN 0xAA /* Sine value × 0x80 */
#define SIGN_BIT 0xAB /* Sign Bit for Hue and Brightness */
#define DSPAUTO 0xAC /* DSP Auto Function ON/OFF Control */
#define DSPAUTO_AWB_EN 0x80 /* AWB auto threshold control */
#define DSPAUTO_DENOISE_EN 0x40 /* De-noise auto threshold control */
#define DSPAUTO_EDGE_EN 0x20 /* Sharpness (edge enhancement) auto strength control */
#define DSPAUTO_UV_EN 0x10 /* UV adjust auto slope control */
#define DSPAUTO_SCAL0_EN 0x08 /* Auto scaling factor control (register SCAL0 (0xA0)) */
#define DSPAUTO_SCAL1_EN 0x04 /* Auto scaling factor control (registers SCAL1 (0xA1 and SCAL2 (0xA2))*/
#define SET_REG(reg, x) (##reg_DEFAULT|x)
#endif //__REG_REGS_H__